{"id":"https://openalex.org/W2113921959","doi":"https://doi.org/10.1109/iscas.2006.1692520","title":"Fast and low-power processor front-end with reduced rename logic circuit complexity","display_name":"Fast and low-power processor front-end with reduced rename logic circuit complexity","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2113921959","doi":"https://doi.org/10.1109/iscas.2006.1692520","mag":"2113921959"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692520","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692520","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048592666","display_name":"R. Sangireddy","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"R. Sangireddy","raw_affiliation_strings":["Department of Electrical Engineering, University of Texas, Dallas, Richardson, TX, USA","Dept. of Electr. Eng., Texas Univ., Richardson, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Texas, Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Texas Univ., Richardson, TX","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5048592666"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.14198445,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8203959465026855},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6169540882110596},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47579750418663025},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4698834717273712},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.4498155415058136},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33069366216659546},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.0779714286327362}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8203959465026855},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6169540882110596},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47579750418663025},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4698834717273712},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.4498155415058136},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33069366216659546},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0779714286327362}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1692520","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692520","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1581311986","https://openalex.org/W1608995421","https://openalex.org/W1874263755","https://openalex.org/W2015691124","https://openalex.org/W2032094184","https://openalex.org/W2081956993","https://openalex.org/W2103405122","https://openalex.org/W2121050483","https://openalex.org/W2123413169","https://openalex.org/W2134370124","https://openalex.org/W2136884213","https://openalex.org/W2137156241","https://openalex.org/W2138351227","https://openalex.org/W2150392806","https://openalex.org/W2151263744","https://openalex.org/W2151345470","https://openalex.org/W2154439782","https://openalex.org/W2161864047","https://openalex.org/W4230658192","https://openalex.org/W4246870635","https://openalex.org/W6636146310"],"related_works":["https://openalex.org/W1657880117","https://openalex.org/W2595172197","https://openalex.org/W2127970246","https://openalex.org/W2084856301","https://openalex.org/W1001352512","https://openalex.org/W4382618745","https://openalex.org/W2885125400","https://openalex.org/W1989889224","https://openalex.org/W1987128138","https://openalex.org/W2748922771"],"abstract_inverted_index":{"With":[0,166],"the":[1,6,11,16,31,40,45,52,60,72,116,121,128,141,148,164],"advent":[2],"of":[3,44,48,64,66,101,118,127,147,182],"clustered":[4],"microarchitectures,":[5],"rename":[7,122,149,174],"map":[8,123,175],"table":[9,176],"at":[10],"front-end":[12,41],"is":[13,42,93,130,133],"shared":[14],"by":[15,194],"clusters,":[17],"and":[18,54,137,145,156,192,197],"hence":[19],"it's":[20],"critical":[21],"path":[22],"delay":[23,157],"should":[24],"not":[25],"become":[26],"a":[27,77,96,110,173,186,212],"bottleneck":[28],"in":[29,39,76,95,120,139,159,169,185,188,204,211],"determining":[30],"processor":[32,214],"clock":[33],"cycle":[34,97],"time.":[35,104],"Also,":[36],"renaming":[37],"logic":[38,162],"one":[43,84],"largest":[46],"contributors":[47],"peak":[49],"temperatures":[50],"on":[51,163],"chip,":[53],"so":[55],"demands":[56],"attention":[57],"to":[58,113,135],"reduce":[59,115],"power":[61],"consumption.":[62],"Analysis":[63],"characteristics":[65],"Spec2000int":[67],"programs":[68,73],"reveals":[69],"that,":[70],"when":[71],"are":[74,208],"processed":[75],"4-wide":[78,213],"(8-wide)":[79],"processor,":[80,172],"none":[81],"or":[82],"only":[83,201],"two-source":[85],"instruction":[86,88],"(an":[87],"with":[89,177,200],"two":[90],"source":[91],"registers)":[92],"renamed":[94],"for":[98],"94%":[99],"(92%)":[100],"total":[102],"execution":[103],"In":[105],"this":[106,167],"paper,":[107],"we":[108],"propose":[109],"novel":[111],"technique":[112,129,168],"significantly":[114],"number":[117],"ports":[119],"table.":[124],"The":[125],"novelty":[126],"that":[131],"it":[132],"easy":[134],"implement":[136],"succeeds":[138],"reducing":[140],"access":[142,189],"time,":[143,190],"power,":[144,154,191],"area":[146,193],"logic,":[150],"without":[151],"any":[152,160],"additional":[153],"area,":[155],"overheads":[158],"other":[161],"chip.":[165],"an":[170],"8-wide":[171],"9":[178],"read":[179],"ports,":[180],"instead":[181],"16,":[183],"results":[184],"reduction":[187],"14%,":[195],"42%,":[196],"49%,":[198],"respectively,":[199],"4.7%":[202],"loss":[203],"IPC.":[205],"Similar":[206],"gains":[207],"also":[209],"seen":[210]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
