{"id":"https://openalex.org/W2141293663","doi":"https://doi.org/10.1109/iscas.2005.1466059","title":"Rapid and Precise Instruction Set Evaluation for Application Specific Processor Design","display_name":"Rapid and Precise Instruction Set Evaluation for Application Specific Processor Design","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2141293663","doi":"https://doi.org/10.1109/iscas.2005.1466059","mag":"2141293663"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1466059","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1466059","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054426512","display_name":"Masaaki MASUDA","orcid":null},"institutions":[{"id":"https://openalex.org/I72253084","display_name":"Saitama University","ror":"https://ror.org/02evnh647","country_code":"JP","type":"education","lineage":["https://openalex.org/I72253084"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"M. Masuda","raw_affiliation_strings":["Department of Elecrical and Electronic Systems, Saitama University, Sakura, Saitama, Japan","Dept. of Elecrical & Electron. Syst., Saitama Univ., Japan"],"affiliations":[{"raw_affiliation_string":"Department of Elecrical and Electronic Systems, Saitama University, Sakura, Saitama, Japan","institution_ids":["https://openalex.org/I72253084"]},{"raw_affiliation_string":"Dept. of Elecrical & Electron. Syst., Saitama Univ., Japan","institution_ids":["https://openalex.org/I72253084"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028917563","display_name":"Kohji Ito","orcid":"https://orcid.org/0000-0001-9573-432X"},"institutions":[{"id":"https://openalex.org/I72253084","display_name":"Saitama University","ror":"https://ror.org/02evnh647","country_code":"JP","type":"education","lineage":["https://openalex.org/I72253084"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Ito","raw_affiliation_strings":["Department of Elecrical and Electronic Systems, Saitama University, Sakura, Saitama, Japan","Dept. of Elecrical & Electron. Syst., Saitama Univ., Japan"],"affiliations":[{"raw_affiliation_string":"Department of Elecrical and Electronic Systems, Saitama University, Sakura, Saitama, Japan","institution_ids":["https://openalex.org/I72253084"]},{"raw_affiliation_string":"Dept. of Elecrical & Electron. Syst., Saitama Univ., Japan","institution_ids":["https://openalex.org/I72253084"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5054426512"],"corresponding_institution_ids":["https://openalex.org/I72253084"],"apc_list":null,"apc_paid":null,"fwci":0.2578,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.60459184,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"41","issue":null,"first_page":"6210","last_page":"6213"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8636534810066223},{"id":"https://openalex.org/keywords/application-specific-instruction-set-processor","display_name":"Application-specific instruction-set processor","score":0.8358091115951538},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.6880419850349426},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5688852667808533},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.5666183829307556},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5374261736869812},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5292168259620667},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.49346840381622314},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4237288236618042},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3997979164123535},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33929315209388733},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.18797260522842407}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8636534810066223},{"id":"https://openalex.org/C201736964","wikidata":"https://www.wikidata.org/wiki/Q621583","display_name":"Application-specific instruction-set processor","level":3,"score":0.8358091115951538},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.6880419850349426},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5688852667808533},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.5666183829307556},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5374261736869812},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5292168259620667},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.49346840381622314},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4237288236618042},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3997979164123535},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33929315209388733},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.18797260522842407},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1466059","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1466059","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2120525597","https://openalex.org/W2134354173","https://openalex.org/W2138447001","https://openalex.org/W2158664566","https://openalex.org/W2171247893","https://openalex.org/W2336285045","https://openalex.org/W3156871676","https://openalex.org/W6677871580","https://openalex.org/W6703529062","https://openalex.org/W6794256084"],"related_works":["https://openalex.org/W1998013902","https://openalex.org/W2036206036","https://openalex.org/W3002622661","https://openalex.org/W37150954","https://openalex.org/W2125503095","https://openalex.org/W2031976241","https://openalex.org/W172453965","https://openalex.org/W4254602588","https://openalex.org/W2094550651","https://openalex.org/W47391476"],"abstract_inverted_index":{"The":[0,80],"selection":[1],"of":[2,5,15,23,70],"instruction":[3,25,50,88],"set":[4,26],"a":[6,33,37,43],"processor":[7,11,34,92],"greatly":[8],"influences":[9],"the":[10,24,53,68,74,83],"hardware":[12],"and":[13,20,47,63,72],"execution":[14,75],"software":[16],"in":[17,31],"speed,":[18],"area,":[19],"power.":[21],"Evaluation":[22],"is":[27,56],"an":[28,60],"important":[29],"task":[30,78],"designing":[32],"specific":[35],"to":[36,45,66],"given":[38,54],"application.":[39],"In":[40],"this":[41],"paper,":[42],"technique":[44,65,85],"rapidly":[46],"precisely":[48],"evaluate":[49],"sets":[51,89],"for":[52,90],"application":[55],"proposed.":[57],"It":[58],"uses":[59],"efficient":[61],"branch":[62],"bound":[64],"explore":[67],"combination":[69],"instructions":[71],"evaluates":[73,87],"steps":[76],"by":[77],"scheduling.":[79],"results":[81],"show":[82],"proposed":[84],"efficiently":[86],"assumed":[91],"hardware.":[93]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}