{"id":"https://openalex.org/W2128822270","doi":"https://doi.org/10.1109/iscas.2005.1466000","title":"Mixed signal and SoC design flow requirements","display_name":"Mixed signal and SoC design flow requirements","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2128822270","doi":"https://doi.org/10.1109/iscas.2005.1466000","mag":"2128822270"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1466000","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1466000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048646582","display_name":"Tuna B. Tar\u0131m","orcid":null},"institutions":[{"id":"https://openalex.org/I117023288","display_name":"Analog Devices (United States)","ror":"https://ror.org/01545pm61","country_code":"US","type":"company","lineage":["https://openalex.org/I117023288"]},{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"T.B. Tarim","raw_affiliation_strings":["Wireless Analog Technology Center, Texas Instrumenits, Inc., Dallas, TX, USA","Wireless Analog Technol. Center, Texas Univ., Dallas, TX, USA"],"affiliations":[{"raw_affiliation_string":"Wireless Analog Technology Center, Texas Instrumenits, Inc., Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111","https://openalex.org/I117023288"]},{"raw_affiliation_string":"Wireless Analog Technol. Center, Texas Univ., Dallas, TX, USA","institution_ids":["https://openalex.org/I117023288"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048646582","display_name":"Tuna B. Tar\u0131m","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]},{"id":"https://openalex.org/I117023288","display_name":"Analog Devices (United States)","ror":"https://ror.org/01545pm61","country_code":"US","type":"company","lineage":["https://openalex.org/I117023288"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T.B. Tarim","raw_affiliation_strings":["Wireless Analog Technology Center, Texas Instrumenits, Inc., Dallas, TX, USA","Wireless Analog Technol. Center, Texas Univ., Dallas, TX, USA"],"affiliations":[{"raw_affiliation_string":"Wireless Analog Technology Center, Texas Instrumenits, Inc., Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111","https://openalex.org/I117023288"]},{"raw_affiliation_string":"Wireless Analog Technol. Center, Texas Univ., Dallas, TX, USA","institution_ids":["https://openalex.org/I117023288"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5048646582"],"corresponding_institution_ids":["https://openalex.org/I117023288","https://openalex.org/I74760111"],"apc_list":null,"apc_paid":null,"fwci":0.2578,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.59715136,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"5974","last_page":"5977"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7685104608535767},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6559044718742371},{"id":"https://openalex.org/keywords/signal-flow-graph","display_name":"Signal-flow graph","score":0.5254769921302795},{"id":"https://openalex.org/keywords/flow","display_name":"Flow (mathematics)","score":0.5051034092903137},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.4939787983894348},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.490100234746933},{"id":"https://openalex.org/keywords/point","display_name":"Point (geometry)","score":0.4431431293487549},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.41841331124305725},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.3804089426994324},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3319854736328125},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.25889962911605835},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2585597634315491},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.17530646920204163},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.13202089071273804},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1023554801940918},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07636600732803345}],"concepts":[{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7685104608535767},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6559044718742371},{"id":"https://openalex.org/C166501922","wikidata":"https://www.wikidata.org/wiki/Q1786523","display_name":"Signal-flow graph","level":2,"score":0.5254769921302795},{"id":"https://openalex.org/C38349280","wikidata":"https://www.wikidata.org/wiki/Q1434290","display_name":"Flow (mathematics)","level":2,"score":0.5051034092903137},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.4939787983894348},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.490100234746933},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.4431431293487549},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.41841331124305725},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.3804089426994324},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3319854736328125},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25889962911605835},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2585597634315491},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.17530646920204163},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.13202089071273804},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1023554801940918},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07636600732803345},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1466000","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1466000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6200000047683716,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1945989198","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2372709865","https://openalex.org/W2017275349","https://openalex.org/W1630910375","https://openalex.org/W2378013451","https://openalex.org/W2128015051","https://openalex.org/W4229489461","https://openalex.org/W268271086","https://openalex.org/W2019635822","https://openalex.org/W2099825670","https://openalex.org/W4242619554"],"abstract_inverted_index":{"The":[0,30],"paper":[1],"addresses":[2],"today's":[3],"mixed":[4],"signal":[5],"and":[6,10,13,22,39,43],"SoC":[7],"design":[8,20],"flow":[9,21],"methodology":[11,23],"issues,":[12],"discusses":[14],"the":[15,25,58],"requirements":[16],"for":[17],"a":[18,33],"successful":[19],"from":[24],"industry":[26],"point":[27],"of":[28,32,60],"view.":[29],"importance":[31,59],"strong":[34],"collaboration":[35],"between":[36],"IP":[37],"owner":[38],"customer,":[40],"maximum":[41],"re-use,":[42],"top":[44],"level":[45],"verification":[46],"(TLV)":[47],"is":[48,54],"discussed":[49],"in":[50,70],"detail.":[51],"An":[52],"example":[53],"given":[55],"to":[56,66],"emphasize":[57],"using":[61],"behavioral":[62],"models":[63],"during":[64],"TLV":[65],"reduce":[67],"simulation":[68],"time":[69],"large":[71],"designs.":[72]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}