{"id":"https://openalex.org/W2169034532","doi":"https://doi.org/10.1109/iscas.2005.1465925","title":"Modeling and Formal Verification of Dataflow Graph in System-Level Design Using Petri net","display_name":"Modeling and Formal Verification of Dataflow Graph in System-Level Design Using Petri net","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2169034532","doi":"https://doi.org/10.1109/iscas.2005.1465925","mag":"2169034532"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465925","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465925","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074578031","display_name":"Tsung-Hsi Chiang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Tsung-Hsi Chiang","raw_affiliation_strings":["Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053658433","display_name":"Lan-Rong Dung","orcid":"https://orcid.org/0000-0002-7231-7029"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Lan-Rong Dung","raw_affiliation_strings":["Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5097459949","display_name":"Ming-Feng Yaung","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ming-Feng Yaung","raw_affiliation_strings":["Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5074578031"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.2578,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.61989796,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"5674","last_page":"5677"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11450","display_name":"Model-Driven Software Engineering Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.7882267832756042},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7863901853561401},{"id":"https://openalex.org/keywords/petri-net","display_name":"Petri net","score":0.7195627689361572},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.628046989440918},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.5783202648162842},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.5461597442626953},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.5123735666275024},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.49764350056648254},{"id":"https://openalex.org/keywords/runtime-verification","display_name":"Runtime verification","score":0.48251602053642273},{"id":"https://openalex.org/keywords/verification","display_name":"Verification","score":0.47720202803611755},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.46684181690216064},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4514261782169342},{"id":"https://openalex.org/keywords/data-flow-analysis","display_name":"Data-flow analysis","score":0.44679781794548035},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.4328182637691498},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.4258458614349365},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.38931840658187866},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.36806803941726685},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.3621594309806824},{"id":"https://openalex.org/keywords/software-system","display_name":"Software system","score":0.29832008481025696},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2891748547554016},{"id":"https://openalex.org/keywords/software-construction","display_name":"Software construction","score":0.10291439294815063},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.09484103322029114}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.7882267832756042},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7863901853561401},{"id":"https://openalex.org/C38677869","wikidata":"https://www.wikidata.org/wiki/Q724168","display_name":"Petri net","level":2,"score":0.7195627689361572},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.628046989440918},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.5783202648162842},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.5461597442626953},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.5123735666275024},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.49764350056648254},{"id":"https://openalex.org/C202973057","wikidata":"https://www.wikidata.org/wiki/Q7380130","display_name":"Runtime verification","level":3,"score":0.48251602053642273},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.47720202803611755},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.46684181690216064},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4514261782169342},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.44679781794548035},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.4328182637691498},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.4258458614349365},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.38931840658187866},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.36806803941726685},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3621594309806824},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.29832008481025696},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2891748547554016},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.10291439294815063},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.09484103322029114},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1465925","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465925","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W54701845","https://openalex.org/W1515231954","https://openalex.org/W1698740054","https://openalex.org/W1999890019","https://openalex.org/W2096455207","https://openalex.org/W2099063334","https://openalex.org/W2099736035","https://openalex.org/W2101129050","https://openalex.org/W2106417701","https://openalex.org/W2108177812","https://openalex.org/W4237568262"],"related_works":["https://openalex.org/W2361881307","https://openalex.org/W2392047570","https://openalex.org/W2035244079","https://openalex.org/W2535719568","https://openalex.org/W1985271980","https://openalex.org/W2135756607","https://openalex.org/W2138343703","https://openalex.org/W2165346564","https://openalex.org/W4255789569","https://openalex.org/W2004066214"],"abstract_inverted_index":{"Formal":[0],"verification":[1,13,42,53,86],"at":[2,14,43],"system-level,":[3],"which":[4,88],"also":[5],"means":[6],"architecture":[7],"verification,":[8],"is":[9,35,79],"different":[10],"from":[11],"functional":[12],"RTL":[15],"level.":[16],"DSP":[17,67],"algorithms":[18],"need":[19],"high-level":[20,52],"transformation":[21],"to":[22,37,108],"achieve":[23],"optimal":[24],"goals":[25],"before":[26],"mapping":[27],"onto":[28],"silicon.":[29],"However,":[30],"a":[31,48,57,66,82],"suitable":[32],"CAD":[33],"tool":[34],"absent":[36],"support":[38],"the":[39,63,71,97,110],"simulation":[40],"and":[41,51,91],"high-level.":[44],"This":[45],"paper":[46],"presents":[47],"novel":[49],"modeling":[50],"methodology":[54],"based":[55],"on":[56],"Petri":[58],"net":[59],"(PN)":[60],"model.":[61,84],"By":[62],"proposed":[64],"method,":[65],"algorithm":[68],"system":[69],"in":[70,96],"form":[72],"of":[73],"FSFG":[74],"(fully":[75],"specified":[76],"flow":[77],"graph)":[78],"transformed":[80],"into":[81],"PN":[83,98],"Moreover,":[85],"methods":[87],"include":[89],"static":[90],"dynamical":[92],"phases":[93],"are":[94],"applied":[95],"domain.":[99],"Finally,":[100],"we":[101],"introduce":[102],"our":[103],"software":[104],"implementation,":[105],"called":[106],"HiVED,":[107],"show":[109],"experimental":[111],"results.":[112]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}