{"id":"https://openalex.org/W2132796854","doi":"https://doi.org/10.1109/iscas.2005.1465910","title":"Delay Modeling of CMOS/CPL Logic Circuits","display_name":"Delay Modeling of CMOS/CPL Logic Circuits","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2132796854","doi":"https://doi.org/10.1109/iscas.2005.1465910","mag":"2132796854"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465910","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465910","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043184259","display_name":"Yuanzhong Wan","orcid":null},"institutions":[{"id":"https://openalex.org/I67031392","display_name":"Carleton University","ror":"https://ror.org/02qtvee93","country_code":"CA","type":"education","lineage":["https://openalex.org/I67031392"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yuanzhong Wan","raw_affiliation_strings":["Department of Electronics, Carleton University, Ottawa, ONT, Canada","Dept. of Electron. Carleton Univ., Ottawa, Ont., Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, Carleton University, Ottawa, ONT, Canada","institution_ids":["https://openalex.org/I67031392"]},{"raw_affiliation_string":"Dept. of Electron. Carleton Univ., Ottawa, Ont., Canada","institution_ids":["https://openalex.org/I67031392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5114097681","display_name":"M. Shams","orcid":null},"institutions":[{"id":"https://openalex.org/I67031392","display_name":"Carleton University","ror":"https://ror.org/02qtvee93","country_code":"CA","type":"education","lineage":["https://openalex.org/I67031392"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"M. Shams","raw_affiliation_strings":["Department of Electronics, Carleton University, Ottawa, ONT, Canada","Dept. of Electron. Carleton Univ., Ottawa, Ont., Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics, Carleton University, Ottawa, ONT, Canada","institution_ids":["https://openalex.org/I67031392"]},{"raw_affiliation_string":"Dept. of Electron. Carleton Univ., Ottawa, Ont., Canada","institution_ids":["https://openalex.org/I67031392"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I67031392"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.19462671,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"5613","last_page":"5616"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7773240804672241},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.7331181168556213},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.672531247138977},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6422828435897827},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6347748041152954},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.6182417273521423},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.607964813709259},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.6045008301734924},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5813817977905273},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.5192790031433105},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5030121207237244},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.4770162105560303},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.47014930844306946},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.42877405881881714},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42612290382385254},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.2996336817741394},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.27593690156936646},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2460242211818695},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.05820685625076294}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7773240804672241},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.7331181168556213},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.672531247138977},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6422828435897827},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6347748041152954},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.6182417273521423},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.607964813709259},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.6045008301734924},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5813817977905273},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.5192790031433105},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5030121207237244},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.4770162105560303},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.47014930844306946},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.42877405881881714},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42612290382385254},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2996336817741394},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27593690156936646},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2460242211818695},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.05820685625076294}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1465910","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465910","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6800000071525574}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2030029202","https://openalex.org/W2140570633","https://openalex.org/W2157024459","https://openalex.org/W2763117154","https://openalex.org/W3103339143","https://openalex.org/W6745528801"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W1977171228","https://openalex.org/W2619968078","https://openalex.org/W2082591327","https://openalex.org/W2066518505","https://openalex.org/W2121963733","https://openalex.org/W2058822291","https://openalex.org/W3210322980","https://openalex.org/W2565020286","https://openalex.org/W1966764473"],"abstract_inverted_index":{"Effective":[0],"optimization":[1],"methods":[2],"aimed":[3],"at":[4],"achieving":[5],"maximal":[6],"speeds":[7],"in":[8],"single-technology":[9],"logic":[10,24],"circuits":[11,20],"are":[12,26],"widely":[13],"available":[14],"but":[15],"systematic":[16],"ways":[17],"suitable":[18],"for":[19,53],"involving":[21],"mixtures":[22],"of":[23,30],"families":[25],"not.":[27],"The":[28],"combination":[29],"standard":[31],"CMOS":[32,54],"with":[33,40],"CPL":[34,60],"(complementary":[35],"pass-transistor":[36],"logic)":[37],"is":[38],"examined":[39],"an":[41],"eye":[42],"to":[43,57],"finding":[44],"the":[45,49],"best":[46,50],"structure":[47],"and":[48,64],"insertion":[51],"points":[52],"buffers":[55],"intended":[56],"improve":[58],"a":[59],"chain's":[61],"propagation":[62],"time":[63],"drive":[65],"capability.":[66]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}