{"id":"https://openalex.org/W2156342621","doi":"https://doi.org/10.1109/iscas.2005.1465869","title":"A Scalable DCO Design for Portable ADPLL Designs","display_name":"A Scalable DCO Design for Portable ADPLL Designs","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2156342621","doi":"https://doi.org/10.1109/iscas.2005.1465869","mag":"2156342621"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465869","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465869","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070037715","display_name":"Chia-Tsun Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chia-Tsun Wu","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100664972","display_name":"Wei Wang","orcid":"https://orcid.org/0000-0002-7206-8659"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei Wang","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005575420","display_name":"I\u2010Chyn Wey","orcid":"https://orcid.org/0000-0003-3412-6958"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"I-Chyn Wey","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109465340","display_name":"An-Yeu Wu","orcid":"https://orcid.org/0000-0003-4731-8633"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"An-Yeu Andy Wu","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","Dept. of Electr. Eng.. Nat. Taiwan Univ., Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Dept. of Electr. Eng.. Nat. Taiwan Univ., Taipei, Taiwan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5070037715"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":1.8141,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.86422351,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"5449","last_page":"5452"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.738621711730957},{"id":"https://openalex.org/keywords/digitally-controlled-oscillator","display_name":"Digitally controlled oscillator","score":0.733916163444519},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6754644513130188},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6209303140640259},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5287237763404846},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4434283673763275},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4346197247505188},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4307166635990143},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.41905534267425537},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.23522642254829407},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22997114062309265},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.19929581880569458}],"concepts":[{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.738621711730957},{"id":"https://openalex.org/C167872736","wikidata":"https://www.wikidata.org/wiki/Q5276224","display_name":"Digitally controlled oscillator","level":5,"score":0.733916163444519},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6754644513130188},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6209303140640259},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5287237763404846},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4434283673763275},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4346197247505188},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4307166635990143},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.41905534267425537},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.23522642254829407},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22997114062309265},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.19929581880569458},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C120164764","wikidata":"https://www.wikidata.org/wiki/Q705396","display_name":"Variable-frequency oscillator","level":4,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas.2005.1465869","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465869","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:140.112.114.62:246246/200704191001420","is_oa":false,"landing_page_url":"http://ntur.lib.ntu.edu.tw//handle/246246/200704191001420","pdf_url":null,"source":{"id":"https://openalex.org/S4306402491","display_name":"NTUR (\u81fa\u7063\u6a5f\u69cb\u5178\u85cf)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I16733864","host_organization_name":"National Taiwan University","host_organization_lineage":["https://openalex.org/I16733864"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.497.7280","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.497.7280","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://access.ee.ntu.edu.tw/Publications/Conference/CA47_2005.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1909887221","https://openalex.org/W2067333289","https://openalex.org/W2079016261","https://openalex.org/W2104362597","https://openalex.org/W2130643847","https://openalex.org/W2143217913","https://openalex.org/W2156550596","https://openalex.org/W4250065533","https://openalex.org/W6640001243","https://openalex.org/W6679579600","https://openalex.org/W6680237377"],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W63276784","https://openalex.org/W2059530328","https://openalex.org/W2156342621","https://openalex.org/W2151657833","https://openalex.org/W2121364018","https://openalex.org/W4235353373","https://openalex.org/W1502098592","https://openalex.org/W2072910550"],"abstract_inverted_index":{"A":[0],"novel":[1],"digital":[2],"controlled":[3],"oscillator":[4],"(DCO)":[5],"design":[6,15,25,34,59],"methodology":[7,16],"is":[8,60],"presented":[9],"in":[10,30,68],"this":[11],"paper.":[12],"The":[13,42,58],"new":[14],"includes":[17],"a":[18,63,69],"scalable":[19],"DCO":[20,37,44],"architecture":[21,45],"and":[22,55],"the":[23,33,47],"developed":[24],"flow.":[26],"With":[27],"precise":[28],"analysis":[29],"early":[31],"stage,":[32],"effort":[35],"of":[36,49],"can":[38],"be":[39],"reduced":[40],"significantly.":[41],"proposed":[43],"has":[46],"characteristics":[48],"high":[50,64],"resolution,":[51],"flexible":[52],"operating":[53],"range,":[54],"easy":[56],"design.":[57],"suitable":[61],"for":[62],"performance":[65],"clock":[66],"generator":[67],"system":[70],"on":[71],"chip":[72],"(SoC)":[73],"application.":[74]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}