{"id":"https://openalex.org/W1939744510","doi":"https://doi.org/10.1109/iscas.2005.1465849","title":"A Re-configurable High-Speed CMOS Track and Latch Comparator with Rail-to-Rail Input for IF Digitization","display_name":"A Re-configurable High-Speed CMOS Track and Latch Comparator with Rail-to-Rail Input for IF Digitization","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W1939744510","doi":"https://doi.org/10.1109/iscas.2005.1465849","mag":"1939744510"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465849","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465849","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089804882","display_name":"H. Pekau","orcid":null},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"H. Pekau","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada","Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada","institution_ids":["https://openalex.org/I168635309"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065969049","display_name":"Lee Hartley","orcid":null},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"L. Hartley","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada","Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada","institution_ids":["https://openalex.org/I168635309"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006013138","display_name":"J.W. Haslett","orcid":"https://orcid.org/0000-0003-2105-3040"},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J.W. Haslett","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada","Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada","institution_ids":["https://openalex.org/I168635309"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada","institution_ids":["https://openalex.org/I168635309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5089804882"],"corresponding_institution_ids":["https://openalex.org/I168635309"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.08185066,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"5369","last_page":"5372"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.9531152248382568},{"id":"https://openalex.org/keywords/comparator-applications","display_name":"Comparator applications","score":0.793921172618866},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.7832672595977783},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6322969794273376},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5597648024559021},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.49100998044013977},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4811174273490906},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.4547204375267029},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.43364205956459045},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.34401848912239075},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2998077869415283},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.27412495017051697},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.08267331123352051}],"concepts":[{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.9531152248382568},{"id":"https://openalex.org/C121649978","wikidata":"https://www.wikidata.org/wiki/Q17007408","display_name":"Comparator applications","level":4,"score":0.793921172618866},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.7832672595977783},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6322969794273376},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5597648024559021},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.49100998044013977},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4811174273490906},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.4547204375267029},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.43364205956459045},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.34401848912239075},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2998077869415283},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.27412495017051697},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.08267331123352051}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1465849","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465849","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7400000095367432,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1580764142","https://openalex.org/W1594101521","https://openalex.org/W1998284495","https://openalex.org/W2106152590","https://openalex.org/W2116549117","https://openalex.org/W2158828648","https://openalex.org/W2162827380","https://openalex.org/W6634615027"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W2104885411","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W2160067645","https://openalex.org/W3123985664","https://openalex.org/W1965786156"],"abstract_inverted_index":{"A":[0],"re-configurable":[1,85],"high":[2],"speed":[3],"track":[4],"and":[5,28,44,70],"latch":[6],"comparator":[7,22,57,76],"with":[8],"rail-to-rail":[9],"input":[10,67],"range":[11],"is":[12,77],"designed":[13],"in":[14,88],"a":[15,34,65,71,80,84],"0.18":[16],"/spl":[17],"mu/m":[18],"CMOS":[19],"process.":[20],"The":[21,37,75],"architecture":[23],"consists":[24],"of":[25,40,48,62],"parallel":[26],"PMOS":[27],"NMOS":[29],"differential":[30,42],"pairs":[31,43],"followed":[32],"by":[33],"regenerative":[35],"latch.":[36],"bias":[38],"current":[39],"the":[41,45,49,56,59],"duty":[46],"cycle":[47],"clock":[50,73],"can":[51],"be":[52],"adjusted":[53],"so":[54],"that":[55],"consumes":[58],"minimum":[60],"amount":[61],"power":[63],"for":[64,83],"given":[66,72],"voltage":[68],"sensitivity":[69],"frequency.":[74],"suitable":[78],"as":[79],"building":[81],"block":[82],"analog-to-digital":[86],"converter":[87],"an":[89],"IF":[90],"digitizing":[91],"software":[92],"radio":[93],"receiver.":[94]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
