{"id":"https://openalex.org/W2157163990","doi":"https://doi.org/10.1109/iscas.2005.1465486","title":"DBNS Addition using Cellular Neural Networks","display_name":"DBNS Addition using Cellular Neural Networks","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2157163990","doi":"https://doi.org/10.1109/iscas.2005.1465486","mag":"2157163990"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465486","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465486","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018727920","display_name":"Youssef Youssry Ibrahim","orcid":null},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Y. Ibrahim","raw_affiliation_strings":["RCIM Research Centre, University of Windsor, Windsor, ONT, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"RCIM Research Centre, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056245742","display_name":"William C. Miller","orcid":"https://orcid.org/0000-0002-1934-7827"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"W.C. Miller","raw_affiliation_strings":["RCIM Research Centre, University of Windsor, Windsor, ONT, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"RCIM Research Centre, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007393900","display_name":"G.A. Jullien","orcid":"https://orcid.org/0009-0009-0911-2926"},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"G.A. Jullien","raw_affiliation_strings":["ATIPS Laboratory, University of Calgary, Calgary, AB, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ATIPS Laboratory, University of Calgary, Calgary, AB, Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037298442","display_name":"Vassil S. Dimitrov","orcid":null},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"V.S. Dimitrov","raw_affiliation_strings":["ATIPS Laboratory, University of Calgary, Calgary, AB, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ATIPS Laboratory, University of Calgary, Calgary, AB, Canada","institution_ids":["https://openalex.org/I168635309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.177,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.81035656,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"50","issue":null,"first_page":"3914","last_page":"3917"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11347","display_name":"Neural Networks Stability and Synchronization","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11347","display_name":"Neural Networks Stability and Synchronization","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8235042095184326},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7481889724731445},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5235478281974792},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.5128819942474365},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4991593360900879},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4660986661911011},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4649326503276825},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.44755321741104126},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.36306315660476685},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35016483068466187},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.23410385847091675},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14665096998214722},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13522905111312866},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10637626051902771},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07638236880302429}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8235042095184326},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7481889724731445},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5235478281974792},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.5128819942474365},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4991593360900879},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4660986661911011},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4649326503276825},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.44755321741104126},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36306315660476685},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35016483068466187},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.23410385847091675},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14665096998214722},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13522905111312866},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10637626051902771},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07638236880302429},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1465486","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465486","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.41999998688697815}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W200398567","https://openalex.org/W571960815","https://openalex.org/W1544808812","https://openalex.org/W1570173134","https://openalex.org/W2056717940","https://openalex.org/W2073618176","https://openalex.org/W2104596554","https://openalex.org/W2107025852","https://openalex.org/W2130416988","https://openalex.org/W2141673477","https://openalex.org/W2160121923","https://openalex.org/W2292208776","https://openalex.org/W2298376400","https://openalex.org/W2916844179"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W2183015194","https://openalex.org/W2389800961","https://openalex.org/W1995389502","https://openalex.org/W2170979950","https://openalex.org/W2039299085"],"abstract_inverted_index":{"This":[0],"paper":[1,48],"introduces":[2],"a":[3,41,51,55,114],"new":[4],"architecture":[5,53],"for":[6,13,54,100],"implementing":[7],"addition":[8],"and":[9,77],"non-zero":[10,85],"digit":[11,86],"reduction":[12],"the":[14,36,68,71,81,95,110,122],"highly":[15],"redundant":[16],"double-base":[17],"number":[18],"system":[19],"(DBNS).":[20],"The":[21,63,88],"circuitry":[22],"is":[23],"realized":[24],"using":[25,90,113],"an":[26],"analog":[27,43,92],"cellular":[28],"neural":[29],"network":[30],"(CNN)":[31],"approach,":[32],"which":[33],"naturally":[34],"maps":[35],"2D":[37,42],"DBNS":[38,56,72],"representation":[39],"to":[40,73,120],"CNN":[44],"architecture.":[45],"In":[46],"this":[47],"we":[49,78],"introduce":[50],"novel":[52],"adder":[57,64],"that":[58],"uses":[59],"no":[60],"digital":[61],"logic.":[62],"exploits":[65],"some":[66],"of":[67,70,97,109,124],"properties":[69],"provide":[74],"limited-carry":[75],"addition,":[76],"also":[79],"address":[80],"problems":[82],"associated":[83],"with":[84],"reduction.":[87],"implementation":[89],"only":[91],"circuits":[93],"has":[94],"advantage":[96],"ultra-low":[98],"noise":[99],"sensitive":[101],"mixed-signal":[102],"circuits.":[103],"We":[104],"present":[105],"circuit":[106],"simulation":[107],"results":[108],"designed":[111],"circuit,":[112],"0.35":[115],"/spl":[116],"mu/m":[117],"CMOS":[118],"technology,":[119],"validate":[121],"feasibility":[123],"our":[125],"technique.":[126]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}