{"id":"https://openalex.org/W2115381319","doi":"https://doi.org/10.1109/iscas.2005.1465403","title":"Performance Analysis by Topology Indexed Lookup Tables","display_name":"Performance Analysis by Topology Indexed Lookup Tables","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2115381319","doi":"https://doi.org/10.1109/iscas.2005.1465403","mag":"2115381319"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465403","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465403","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027214075","display_name":"Priyanka Agarwal","orcid":null},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Agarwal","raw_affiliation_strings":["SUNY Binghamton CSD, USA","Sun MicroSystems, Inc.orporated, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SUNY Binghamton CSD, USA","institution_ids":["https://openalex.org/I123946342"]},{"raw_affiliation_string":"Sun MicroSystems, Inc.orporated, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059631441","display_name":"A. Vidyarthi","orcid":null},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Vidyarthi","raw_affiliation_strings":["SUNY Binghamton CSD, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SUNY Binghamton CSD, USA","institution_ids":["https://openalex.org/I123946342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074401951","display_name":"Patrick H. Madden","orcid":"https://orcid.org/0000-0002-1727-6885"},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P.H. Madden","raw_affiliation_strings":["SUNY Binghamton CSD, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SUNY Binghamton CSD, USA","institution_ids":["https://openalex.org/I123946342"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I123946342"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"3579","last_page":"3582"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8726294040679932},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7993993759155273},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7362834215164185},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6680659055709839},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6114988923072815},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.6038638353347778},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5319246053695679},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.502025842666626},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47656726837158203},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4117482602596283},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3563622236251831},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1916004717350006},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1908518671989441},{"id":"https://openalex.org/keywords/data-mining","display_name":"Data mining","score":0.13425031304359436},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11639264225959778},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.06875672936439514}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8726294040679932},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7993993759155273},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7362834215164185},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6680659055709839},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6114988923072815},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.6038638353347778},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5319246053695679},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.502025842666626},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47656726837158203},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4117482602596283},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3563622236251831},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1916004717350006},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1908518671989441},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.13425031304359436},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11639264225959778},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.06875672936439514},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2005.1465403","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465403","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.73.5613","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.73.5613","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://vlsicad.cs.binghamton.edu/~pmadden/pubs/Agarwal05.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1603813963","https://openalex.org/W1984588379","https://openalex.org/W2041990192","https://openalex.org/W2076265641","https://openalex.org/W2111491016","https://openalex.org/W2123692429","https://openalex.org/W2129155040","https://openalex.org/W2142356348","https://openalex.org/W2154363431","https://openalex.org/W2163626738","https://openalex.org/W2179314520","https://openalex.org/W4243803198","https://openalex.org/W6676609848"],"related_works":["https://openalex.org/W2204879205","https://openalex.org/W2096437374","https://openalex.org/W1943174035","https://openalex.org/W1928481607","https://openalex.org/W3135165657","https://openalex.org/W1485582195","https://openalex.org/W2107551409","https://openalex.org/W4249541960","https://openalex.org/W4388667102","https://openalex.org/W2080035745"],"abstract_inverted_index":{"Accurate":[0],"analysis":[1],"of":[2,13,49,59,78],"VLSI":[3],"interconnects":[4],"is":[5,64],"essential":[6],"to":[7,54],"the":[8,47],"performance-driven":[9],"synthesis":[10],"and":[11,35,72],"layout":[12],"integrated":[14],"circuits.":[15],"Existing":[16],"techniques":[17],"are":[18,30],"based":[19,65],"on":[20,66],"either":[21],"simulation,":[22],"analytic":[23],"formulas,":[24],"or":[25],"small-scale":[26],"table":[27],"lookup.":[28],"There":[29],"tradeoffs":[31],"in":[32,57],"compute":[33],"time":[34],"accuracy.":[36],"In":[37],"this":[38],"paper,":[39],"we":[40],"present":[41],"an":[42],"effective":[43],"approach":[44],"which":[45],"captures":[46],"accuracy":[48],"SPICE":[50],"while":[51],"remaining":[52],"close":[53],"Elmore":[55],"delay":[56],"terms":[58],"computational":[60],"overhead.":[61],"Our":[62],"method":[63],"topology":[67],"indexed":[68],"lookup":[69],"tables":[70],"(TILT),":[71],"uses":[73],"a":[74],"extremely":[75],"large":[76],"database":[77],"precomputed":[79],"values.":[80]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}