{"id":"https://openalex.org/W2128872032","doi":"https://doi.org/10.1109/iscas.2005.1465346","title":"HIBI-based Multiprocessor SoC on FPGA","display_name":"HIBI-based Multiprocessor SoC on FPGA","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2128872032","doi":"https://doi.org/10.1109/iscas.2005.1465346","mag":"2128872032"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465346","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465346","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078390067","display_name":"Erno Salminen","orcid":null},"institutions":[{"id":"https://openalex.org/I150589677","display_name":"Tampere University of Applied Sciences","ror":"https://ror.org/00bwtjf83","country_code":"FI","type":"education","lineage":["https://openalex.org/I150589677"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":true,"raw_author_name":"E. Salminen","raw_affiliation_strings":["Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","Inst, of Digital & Comput. Syst., Tampere Univ. of Technol., Finland"],"affiliations":[{"raw_affiliation_string":"Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Inst, of Digital & Comput. Syst., Tampere Univ. of Technol., Finland","institution_ids":["https://openalex.org/I150589677"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033576751","display_name":"Ari Kulmala","orcid":"https://orcid.org/0009-0005-5755-7402"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]},{"id":"https://openalex.org/I150589677","display_name":"Tampere University of Applied Sciences","ror":"https://ror.org/00bwtjf83","country_code":"FI","type":"education","lineage":["https://openalex.org/I150589677"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"A. Kulmala","raw_affiliation_strings":["Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","Inst, of Digital & Comput. Syst., Tampere Univ. of Technol., Finland"],"affiliations":[{"raw_affiliation_string":"Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Inst, of Digital & Comput. Syst., Tampere Univ. of Technol., Finland","institution_ids":["https://openalex.org/I150589677"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102937415","display_name":"Timo D. H\u00e4m\u00e4l\u00e4inen","orcid":"https://orcid.org/0000-0002-7867-0800"},"institutions":[{"id":"https://openalex.org/I150589677","display_name":"Tampere University of Applied Sciences","ror":"https://ror.org/00bwtjf83","country_code":"FI","type":"education","lineage":["https://openalex.org/I150589677"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"T.D. Hamalainen","raw_affiliation_strings":["Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","Inst, of Digital & Comput. Syst., Tampere Univ. of Technol., Finland"],"affiliations":[{"raw_affiliation_string":"Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Inst, of Digital & Comput. Syst., Tampere Univ. of Technol., Finland","institution_ids":["https://openalex.org/I150589677"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5078390067"],"corresponding_institution_ids":["https://openalex.org/I150589677","https://openalex.org/I4210133110"],"apc_list":null,"apc_paid":null,"fwci":4.1528,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.94765921,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"3351","last_page":"3354"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7776426076889038},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7265676856040955},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6822857856750488},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6316710710525513},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6280710697174072},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.6093109846115112},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6032835245132446},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.46033912897109985},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4477602243423462},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39814338088035583},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3450024724006653},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.20971298217773438}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7776426076889038},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7265676856040955},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6822857856750488},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6316710710525513},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6280710697174072},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.6093109846115112},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6032835245132446},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.46033912897109985},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4477602243423462},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39814338088035583},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3450024724006653},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.20971298217773438},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1465346","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465346","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322862","display_name":"Ulla Tuomisen S\u00e4\u00e4ti\u00f6","ror":"https://ror.org/0066s0r72"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1863888138","https://openalex.org/W1874569663","https://openalex.org/W2118785102","https://openalex.org/W2139930253","https://openalex.org/W2152099665","https://openalex.org/W2160457411","https://openalex.org/W2534992321","https://openalex.org/W2537556459","https://openalex.org/W4245397077","https://openalex.org/W4252257803"],"related_works":["https://openalex.org/W2187189666","https://openalex.org/W2949084706","https://openalex.org/W1509155667","https://openalex.org/W2518118925","https://openalex.org/W2520291760","https://openalex.org/W3208151864","https://openalex.org/W2391376741","https://openalex.org/W1976459683","https://openalex.org/W1564576805","https://openalex.org/W4254372399"],"abstract_inverted_index":{"An":[0],"FPGA":[1,26,118],"offers":[2],"an":[3,52],"excellent":[4],"platform":[5],"for":[6],"a":[7,43,73,77],"system-on-chip":[8],"consisting":[9],"of":[10,63,75,100,127],"intellectual":[11],"property":[12],"(IP)":[13],"blocks.":[14],"The":[15,91,120],"problem":[16,40],"is":[17,87,114,124],"that":[18],"IP":[19,32,48,59],"blocks":[20],"and":[21,47,85,102],"their":[22],"interconnections":[23],"are":[24],"often":[25],"vendor":[27],"dependent.":[28],"Our":[29],"HIBI":[30,86,137],"(heterogeneous":[31],"block":[33,49],"interconnection)":[34],"network-on-chip":[35],"(NoC)":[36],"scheme":[37],"solves":[38],"the":[39,109,128,140],"by":[41],"providing":[42],"flexible":[44],"interconnection":[45,135],"network":[46],"integration":[50,145],"with":[51,80],"open":[53],"core":[54],"protocol":[55],"(OCP)":[56],"interface.":[57],"Therefore,":[58],"components":[60],"can":[61],"be":[62],"any":[64],"type:":[65],"processors;":[66],"hardware":[67],"accelerators;":[68],"communication":[69],"interfaces;":[70],"memories.":[71],"As":[72],"proof":[74],"concept,":[76],"multiprocessor":[78],"system":[79,93,133],"eight":[81],"soft":[82],"processor":[83],"cores":[84],"prototyped":[88],"on":[89,108],"FPGA.":[90,147],"whole":[92],"uses":[94],"36,402":[95],"logic":[96],"elements,":[97],"2.9":[98],"Mbits":[99],"RAM,":[101],"operates":[103],"at":[104],"78":[105],"MHz":[106],"frequency":[107],"Altera":[110],"Stratix":[111],"1S40,":[112],"which":[113],"comparable":[115],"to":[116,132],"other":[117],"multiprocessors.":[119],"most":[121],"important":[122],"benefit":[123],"significant":[125],"reduction":[126],"design":[129],"effort":[130],"compared":[131],"specific":[134],"networks.":[136],"also":[138],"presents":[139],"first":[141],"OCP":[142],"compliant":[143],"IP-block":[144],"in":[146]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}