{"id":"https://openalex.org/W2161018999","doi":"https://doi.org/10.1109/iscas.2005.1465207","title":"Effective Capacitance for Gate Delay with RC Loads","display_name":"Effective Capacitance for Gate Delay with RC Loads","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2161018999","doi":"https://doi.org/10.1109/iscas.2005.1465207","mag":"2161018999"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465207","is_oa":false,"landing_page_url":"http://doi.org/10.1109/iscas.2005.1465207","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075175558","display_name":"Zhangcai Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Zhang-cai Huang","raw_affiliation_strings":["[Waseda University, Fukuoka, Japan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"[Waseda University, Fukuoka, Japan]","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108583073","display_name":"A. Kurokawa","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"A. Kurokawa","raw_affiliation_strings":["[Waseda University, Fukuoka, Japan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"[Waseda University, Fukuoka, Japan]","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101401697","display_name":"Yoshiyuki Inoue","orcid":"https://orcid.org/0000-0002-7272-1136"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Y. Inoue","raw_affiliation_strings":["[Waseda University, Fukuoka, Japan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"[Waseda University, Fukuoka, Japan]","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0903,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.80779695,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"2795","last_page":"2798"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.8092739582061768},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.5045684576034546},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.44555121660232544},{"id":"https://openalex.org/keywords/parasitic-capacitance","display_name":"Parasitic capacitance","score":0.44091659784317017},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.40968960523605347},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3852594494819641},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3591681122779846},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.35254761576652527},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2335619032382965},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16156527400016785},{"id":"https://openalex.org/keywords/electrode","display_name":"Electrode","score":0.1115705668926239}],"concepts":[{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.8092739582061768},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.5045684576034546},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.44555121660232544},{"id":"https://openalex.org/C154318817","wikidata":"https://www.wikidata.org/wiki/Q2157249","display_name":"Parasitic capacitance","level":4,"score":0.44091659784317017},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.40968960523605347},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3852594494819641},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3591681122779846},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.35254761576652527},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2335619032382965},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16156527400016785},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.1115705668926239},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1465207","is_oa":false,"landing_page_url":"http://doi.org/10.1109/iscas.2005.1465207","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7400000095367432}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1991973217","https://openalex.org/W2006097283","https://openalex.org/W2108816571","https://openalex.org/W2127012121","https://openalex.org/W2131168529","https://openalex.org/W2131751530","https://openalex.org/W2133276614","https://openalex.org/W2135895868","https://openalex.org/W2142896025","https://openalex.org/W2143096499","https://openalex.org/W2163755955","https://openalex.org/W4242813950","https://openalex.org/W4245501382","https://openalex.org/W6684482238"],"related_works":["https://openalex.org/W2394034449","https://openalex.org/W2051045034","https://openalex.org/W2904654231","https://openalex.org/W2999380399","https://openalex.org/W2910612019","https://openalex.org/W4210807885","https://openalex.org/W2248915580","https://openalex.org/W2059163921","https://openalex.org/W4304890870","https://openalex.org/W2126779451"],"abstract_inverted_index":{"In":[0,37,59],"deep":[1],"submicron":[2],"designs,":[3],"the":[4,13,31,45,52,55,62,70,80,97,123],"resistance":[5],"of":[6,16,21,54,72,82,108],"interconnect":[7,35],"plays":[8],"a":[9,40,109],"dominant":[10],"role":[11],"on":[12],"timing":[14],"behavior":[15],"logic":[17],"gates.":[18],"The":[19],"concept":[20],"effective":[22,73,83],"capacitance":[23,74,84],"C/sub":[24,47,92],"eff/":[25,48,93],"is":[26,49,57,65,75,85,94,102,119],"usually":[27],"used":[28],"to":[29,43,87],"calculate":[30],"gate":[32,111],"delay":[33],"for":[34,104],"loads.":[36,114],"this":[38],"paper,":[39],"new":[41],"method":[42],"derive":[44],"expression":[46,56,71],"presented,":[50],"and":[51,77],"accuracy":[53],"discussed.":[58],"our":[60],"approach,":[61],"output":[63,88,106],"waveform":[64],"assumed":[66],"as":[67],"linear.":[68],"Thus,":[69],"simple":[76],"efficient.":[78],"Moreover,":[79],"result":[81],"insensitive":[86],"wave":[89],"shape":[90],"because":[91],"determined":[95],"by":[96],"curve":[98],"area.":[99],"Therefore,":[100],"it":[101,118],"appropriate":[103],"various":[105],"waveforms":[107],"CMOS":[110],"with":[112,122],"RC":[113],"Experimental":[115],"results":[116],"show":[117],"in":[120],"agreement":[121],"Spice":[124],"simulation.":[125]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
