{"id":"https://openalex.org/W2153940514","doi":"https://doi.org/10.1109/iscas.2005.1465124","title":"Timing Yield Estimation Using Statistical Static Timing Analysis","display_name":"Timing Yield Estimation Using Statistical Static Timing Analysis","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2153940514","doi":"https://doi.org/10.1109/iscas.2005.1465124","mag":"2153940514"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465124","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465124","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113424838","display_name":"Min Pan","orcid":"https://orcid.org/0000-0002-2552-1086"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Min Pan","raw_affiliation_strings":["ECE Department, Iowa State University, USA"],"affiliations":[{"raw_affiliation_string":"ECE Department, Iowa State University, USA","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101613339","display_name":"Chris Chu","orcid":"https://orcid.org/0000-0001-6073-1719"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chris Chong-Nuen Chu","raw_affiliation_strings":["ECE Department, Iowa State University, USA"],"affiliations":[{"raw_affiliation_string":"ECE Department, Iowa State University, USA","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010044705","display_name":"Haidong Zhou","orcid":"https://orcid.org/0000-0002-1595-1912"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hai Zhou","raw_affiliation_strings":["ECE Department, Northwestern University, USA"],"affiliations":[{"raw_affiliation_string":"ECE Department, Northwestern University, USA","institution_ids":["https://openalex.org/I111979921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5113424838"],"corresponding_institution_ids":["https://openalex.org/I173911158"],"apc_list":null,"apc_paid":null,"fwci":2.9021,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.91101032,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"2461","last_page":"2464"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.8621463775634766},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.727195143699646},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.639341413974762},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6388002634048462},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.617129385471344},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.529875636100769},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5230811238288879},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4527556598186493},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4364580810070038},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4278483986854553},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4118579924106598},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.3076057732105255},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2611082196235657},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11409929394721985},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.10574597120285034},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.07725363969802856}],"concepts":[{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.8621463775634766},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.727195143699646},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.639341413974762},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6388002634048462},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.617129385471344},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.529875636100769},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5230811238288879},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4527556598186493},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4364580810070038},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4278483986854553},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4118579924106598},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.3076057732105255},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2611082196235657},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11409929394721985},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.10574597120285034},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.07725363969802856},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2005.1465124","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465124","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.83.1355","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.83.1355","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://home.eng.iastate.edu/~cnchu/pubs/c27.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W61749477","https://openalex.org/W2062907832","https://openalex.org/W2098213448","https://openalex.org/W2101264278","https://openalex.org/W2106565868","https://openalex.org/W2120116751","https://openalex.org/W2121334524","https://openalex.org/W2123512677","https://openalex.org/W2126564504","https://openalex.org/W2128090256","https://openalex.org/W2143514594","https://openalex.org/W2144436020","https://openalex.org/W2149447807","https://openalex.org/W2152486274","https://openalex.org/W2158750015","https://openalex.org/W4236222489","https://openalex.org/W4237955880","https://openalex.org/W4253814782","https://openalex.org/W4253856301","https://openalex.org/W4254506919","https://openalex.org/W6602489599","https://openalex.org/W6680808887"],"related_works":["https://openalex.org/W2116259070","https://openalex.org/W2116514610","https://openalex.org/W2163318442","https://openalex.org/W2003180247","https://openalex.org/W3201048403","https://openalex.org/W2123512677","https://openalex.org/W2011677428","https://openalex.org/W2128528443","https://openalex.org/W4232019485","https://openalex.org/W2144282137"],"abstract_inverted_index":{"As":[0],"process":[1,79,136],"variations":[2,130,137],"become":[3],"a":[4,11,51,83],"significant":[5],"problem":[6,45],"in":[7,98,118],"deep":[8],"sub-micron":[9],"technology,":[10],"shift":[12],"from":[13],"deterministic":[14],"static":[15,20],"timing":[16,21,37,43,88,104,148],"analysis":[17,22],"to":[18,54,78,85,135],"statistical":[19,52],"for":[23,46],"high-performance":[24],"circuit":[25,100,142],"designs":[26],"could":[27,145],"reduce":[28],"the":[29,42,59,87,92,99,103,147,153],"excessive":[30],"conservatism":[31],"that":[32,127],"is":[33,161],"built":[34],"into":[35],"current":[36],"design":[38],"methods.":[39],"We":[40,57,81],"address":[41],"yield":[44,89,105,149],"sequential":[47],"circuits":[48],"and":[49,61,70,74,131,157],"propose":[50,82],"approach":[53,110],"handle":[55],"it.":[56],"consider":[58],"spatial":[60],"path":[62,66,129,159],"reconvergence":[63],"correlations":[64],"between":[65,155],"delays,":[67],"set-up":[68],"time":[69,72],"hold":[71],"constraints,":[73],"clock":[75,132],"skew":[76,133],"due":[77,134],"variations.":[80],"method":[84],"get":[86],"based":[90],"on":[91,141],"delay":[93],"distributions":[94],"of":[95,114],"register-to-register":[96],"paths":[97],"On":[101],"average,":[102],"results":[106,125],"obtained":[107],"by":[108],"our":[109],"have":[111,138],"average":[112],"errors":[113],"less":[115],"than":[116],"1.0%":[117],"comparison":[119],"with":[120],"Monte":[121],"Carlo":[122],"simulation.":[123],"Experimental":[124],"show":[126],"shortest":[128,158],"considerable":[139],"impact":[140],"timing,":[143],"which":[144],"bias":[146],"results.":[150],"In":[151],"addition,":[152],"correlation":[154],"longest":[156],"delays":[160],"not":[162],"significant.":[163]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}