{"id":"https://openalex.org/W2121875468","doi":"https://doi.org/10.1109/iscas.2005.1465059","title":"Digital Built-in Self-Test of CMOS Analog Iterative Decoders","display_name":"Digital Built-in Self-Test of CMOS Analog Iterative Decoders","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2121875468","doi":"https://doi.org/10.1109/iscas.2005.1465059","mag":"2121875468"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465059","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465059","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006937607","display_name":"Mimi Yiu","orcid":null},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mimi Yiu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","Dept. of Electr. & Comput. Eng, Alberta Univ., Edmonton, Alta., Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Alberta Univ., Edmonton, Alta., Canada","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024704337","display_name":"Vincent Gaudet","orcid":"https://orcid.org/0000-0002-5534-0825"},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"V.C. Gaudet","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003187523","display_name":"Christian Schlegel","orcid":"https://orcid.org/0000-0002-6493-5548"},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"C. Schlegel","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103171582","display_name":"Chris Winstead","orcid":"https://orcid.org/0000-0001-5238-5852"},"institutions":[{"id":"https://openalex.org/I121980950","display_name":"Utah State University","ror":"https://ror.org/00h6set76","country_code":"US","type":"education","lineage":["https://openalex.org/I121980950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Winstead","raw_affiliation_strings":["Utah State University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Utah State University, USA","institution_ids":["https://openalex.org/I121980950"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4422,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.60251046,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"2204","last_page":"2207"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12029","display_name":"DNA and Biological Computing","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.8229067325592041},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6990222930908203},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.6605641841888428},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.630509614944458},{"id":"https://openalex.org/keywords/hamming-code","display_name":"Hamming code","score":0.4673830568790436},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44987809658050537},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4369737207889557},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4311385750770569},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4141278862953186},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.31786036491394043},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2872391939163208},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20151549577713013},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1637783646583557},{"id":"https://openalex.org/keywords/block-code","display_name":"Block code","score":0.07665017247200012}],"concepts":[{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.8229067325592041},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6990222930908203},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.6605641841888428},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.630509614944458},{"id":"https://openalex.org/C73150493","wikidata":"https://www.wikidata.org/wiki/Q853922","display_name":"Hamming code","level":4,"score":0.4673830568790436},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44987809658050537},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4369737207889557},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4311385750770569},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4141278862953186},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.31786036491394043},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2872391939163208},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20151549577713013},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1637783646583557},{"id":"https://openalex.org/C157125643","wikidata":"https://www.wikidata.org/wiki/Q884707","display_name":"Block code","level":3,"score":0.07665017247200012},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2005.1465059","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465059","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.108.2725","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.108.2725","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.neng.usu.edu/ece/faculty/winstead/papers/Yiu-ISCAS-2005.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1506510405","https://openalex.org/W1574245747","https://openalex.org/W2002281765","https://openalex.org/W2114726247","https://openalex.org/W2115434953","https://openalex.org/W2121606987","https://openalex.org/W2128765501","https://openalex.org/W2137813581","https://openalex.org/W2144814304","https://openalex.org/W2152279620","https://openalex.org/W2165851609","https://openalex.org/W2987657883","https://openalex.org/W3152750074","https://openalex.org/W4300188436","https://openalex.org/W6630252971","https://openalex.org/W6634359839"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2165367082","https://openalex.org/W1972641423","https://openalex.org/W611446063","https://openalex.org/W1996322406","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W4206938017","https://openalex.org/W1967064512","https://openalex.org/W2388299947"],"abstract_inverted_index":{"A":[0,46,73],"design":[1],"method":[2],"is":[3,64,79,85],"presented":[4],"for":[5,52,87],"testing":[6],"of":[7,66,76],"analog":[8,35],"iterative":[9,36,89],"decoders":[10,37],"using":[11,30,58,91],"digital":[12,32,44,82],"built-in":[13],"self-test":[14],"(BIST).":[15],"Mixed-signal":[16],"BIST":[17,33,47,83],"schemes":[18],"are":[19],"often":[20],"complex":[21],"and":[22,50],"demand":[23],"larger":[24],"than":[25],"acceptable":[26],"hardware":[27],"cost.":[28],"By":[29],"a":[31],"scheme,":[34],"can":[38],"easily":[39],"be":[40],"tested":[41],"in":[42,70],"the":[43,71,92],"domain.":[45],"was":[48],"designed":[49],"simulated":[51],"an":[53],"(8,4,4)":[54],"extended":[55],"Hamming":[56],"decoder":[57,90],"0.18":[59],"/spl":[60],"mu/m":[61],"CMOS.":[62],"It":[63],"capable":[65],"detecting":[67],"transistor":[68],"faults":[69],"decoder.":[72],"decoding":[74],"rate":[75],"444":[77],"kbps":[78],"achieved.":[80],"The":[81],"scheme":[84],"suitable":[86],"any":[88],"sum-product":[93],"algorithm.":[94]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}