{"id":"https://openalex.org/W2129105027","doi":"https://doi.org/10.1109/iscas.2005.1465006","title":"Wave Log-Domain Filters","display_name":"Wave Log-Domain Filters","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2129105027","doi":"https://doi.org/10.1109/iscas.2005.1465006","mag":"2129105027"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465006","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465006","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078131146","display_name":"M.A. Teplechuk","orcid":null},"institutions":[{"id":"https://openalex.org/I7882870","display_name":"University of Glasgow","ror":"https://ror.org/00vtgdb53","country_code":"GB","type":"education","lineage":["https://openalex.org/I7882870"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"M.A. Teplechuk","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow, UK","Dept. of Electron. & Electr. Eng., Glasgow Univ., UK#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow, UK","institution_ids":["https://openalex.org/I7882870"]},{"raw_affiliation_string":"Dept. of Electron. & Electr. Eng., Glasgow Univ., UK#TAB#","institution_ids":["https://openalex.org/I7882870"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048796037","display_name":"J.I. Sewell","orcid":"https://orcid.org/0000-0001-9701-377X"},"institutions":[{"id":"https://openalex.org/I7882870","display_name":"University of Glasgow","ror":"https://ror.org/00vtgdb53","country_code":"GB","type":"education","lineage":["https://openalex.org/I7882870"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"J.I. Sewell","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow, UK","Dept. of Electron. & Electr. Eng., Glasgow Univ., UK#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow, UK","institution_ids":["https://openalex.org/I7882870"]},{"raw_affiliation_string":"Dept. of Electron. & Electr. Eng., Glasgow Univ., UK#TAB#","institution_ids":["https://openalex.org/I7882870"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5078131146"],"corresponding_institution_ids":["https://openalex.org/I7882870"],"apc_list":null,"apc_paid":null,"fwci":0.3012,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.65300938,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":null,"first_page":"1992","last_page":"1995"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bicmos","display_name":"BiCMOS","score":0.7007360458374023},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6124482154846191},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.5575185418128967},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.5476618409156799},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5430019497871399},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.520643413066864},{"id":"https://openalex.org/keywords/network-synthesis-filters","display_name":"Network synthesis filters","score":0.5106659531593323},{"id":"https://openalex.org/keywords/heterojunction-bipolar-transistor","display_name":"Heterojunction bipolar transistor","score":0.49310776591300964},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4879536032676697},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.412850558757782},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3239845037460327},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3215883672237396},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.13289359211921692},{"id":"https://openalex.org/keywords/bipolar-junction-transistor","display_name":"Bipolar junction transistor","score":0.12342056632041931},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07584869861602783}],"concepts":[{"id":"https://openalex.org/C62427370","wikidata":"https://www.wikidata.org/wiki/Q173416","display_name":"BiCMOS","level":4,"score":0.7007360458374023},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6124482154846191},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.5575185418128967},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.5476618409156799},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5430019497871399},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.520643413066864},{"id":"https://openalex.org/C51297928","wikidata":"https://www.wikidata.org/wiki/Q7001207","display_name":"Network synthesis filters","level":2,"score":0.5106659531593323},{"id":"https://openalex.org/C173408217","wikidata":"https://www.wikidata.org/wiki/Q1428898","display_name":"Heterojunction bipolar transistor","level":5,"score":0.49310776591300964},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4879536032676697},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.412850558757782},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3239845037460327},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3215883672237396},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.13289359211921692},{"id":"https://openalex.org/C23061349","wikidata":"https://www.wikidata.org/wiki/Q188946","display_name":"Bipolar junction transistor","level":4,"score":0.12342056632041931},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07584869861602783},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2005.1465006","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465006","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:eprints.gla.ac.uk:31716","is_oa":false,"landing_page_url":"http://eprints.gla.ac.uk/31716/","pdf_url":null,"source":{"id":"https://openalex.org/S4210235606","display_name":"ENLIGHTEN (Jurnal Bimbingan dan Konseling Islam)","issn_l":"2622-8912","issn":["2622-8912","2622-8920"],"is_oa":false,"is_in_doaj":true,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference Proceedings"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1871892935","https://openalex.org/W2005838462","https://openalex.org/W2066110005","https://openalex.org/W2075735747","https://openalex.org/W2098342684","https://openalex.org/W2109266049","https://openalex.org/W2146439891","https://openalex.org/W2156396306","https://openalex.org/W2164798594","https://openalex.org/W2167193229","https://openalex.org/W2332328844","https://openalex.org/W6639416875","https://openalex.org/W6684725225"],"related_works":["https://openalex.org/W1492027935","https://openalex.org/W2140183546","https://openalex.org/W1544173589","https://openalex.org/W2537721720","https://openalex.org/W4387933462","https://openalex.org/W2140681148","https://openalex.org/W1943862574","https://openalex.org/W2154960098","https://openalex.org/W2555993941","https://openalex.org/W1586292687"],"abstract_inverted_index":{"A":[0],"novel":[1],"approach":[2],"to":[3,58],"designing":[4],"wave":[5,13],"filters":[6],"in":[7],"the":[8],"log-domain":[9,38],"is":[10,22,28],"presented.":[11],"Several":[12],"two-port":[14],"topologies":[15],"are":[16,56],"investigated,":[17],"and":[18,36,48],"a":[19],"performance":[20],"comparison":[21],"carried":[23],"out.":[24],"The":[25,61],"design":[26,62,70],"feasibility":[27],"illustrated":[29],"on":[30],"three":[31],"examples":[32],"both":[33],"for":[34],"HBT":[35],"MOSFET":[37],"filters;":[39],"IHP":[40],"0.25":[41],"/spl":[42,50],"mu/m":[43,51],"SiGe":[44],"BiCMOS":[45],"process":[46],"parameters":[47],"0.35":[49],"BSIM3v3":[52],"CMOS":[53],"model,":[54],"respectively,":[55],"used":[57],"perform":[59],"simulation.":[60],"procedure":[63],"has":[64],"been":[65],"fully":[66],"incorporated":[67],"into":[68],"XFILTER":[69],"software.":[71]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}