{"id":"https://openalex.org/W2095820153","doi":"https://doi.org/10.1109/iscas.2005.1464971","title":"A Distributed FIFO Scheme for on Chip Communication","display_name":"A Distributed FIFO Scheme for on Chip Communication","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2095820153","doi":"https://doi.org/10.1109/iscas.2005.1464971","mag":"2095820153"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1464971","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464971","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111896578","display_name":"R.R. Rydberg","orcid":null},"institutions":[{"id":"https://openalex.org/I72951846","display_name":"Washington State University","ror":"https://ror.org/05dk0ce17","country_code":"US","type":"education","lineage":["https://openalex.org/I72951846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R.R. Rydberg","raw_affiliation_strings":["School of EECS, Washington State University, Pullman, WA, USA","Sch. of EECS, Washington State Univ., Pullman, WA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of EECS, Washington State University, Pullman, WA, USA","institution_ids":["https://openalex.org/I72951846"]},{"raw_affiliation_string":"Sch. of EECS, Washington State Univ., Pullman, WA, USA","institution_ids":["https://openalex.org/I72951846"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077134354","display_name":"Jabulani Nyathi","orcid":"https://orcid.org/0000-0003-2822-3604"},"institutions":[{"id":"https://openalex.org/I72951846","display_name":"Washington State University","ror":"https://ror.org/05dk0ce17","country_code":"US","type":"education","lineage":["https://openalex.org/I72951846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Nyathi","raw_affiliation_strings":["School of EECS, Washington State University, Pullman, WA, USA","Sch. of EECS, Washington State Univ., Pullman, WA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of EECS, Washington State University, Pullman, WA, USA","institution_ids":["https://openalex.org/I72951846"]},{"raw_affiliation_string":"Sch. of EECS, Washington State Univ., Pullman, WA, USA","institution_ids":["https://openalex.org/I72951846"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057615824","display_name":"J.G. Delgado-Frias","orcid":"https://orcid.org/0000-0002-7026-9991"},"institutions":[{"id":"https://openalex.org/I72951846","display_name":"Washington State University","ror":"https://ror.org/05dk0ce17","country_code":"US","type":"education","lineage":["https://openalex.org/I72951846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.G. Delgado-Frias","raw_affiliation_strings":["School of EECS, Washington State University, Pullman, WA, USA","Sch. of EECS, Washington State Univ., Pullman, WA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of EECS, Washington State University, Pullman, WA, USA","institution_ids":["https://openalex.org/I72951846"]},{"raw_affiliation_string":"Sch. of EECS, Washington State Univ., Pullman, WA, USA","institution_ids":["https://openalex.org/I72951846"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I72951846"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1851","last_page":"1854"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6876364946365356},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.6595445871353149},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.5671924948692322},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5475167632102966},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.52838134765625},{"id":"https://openalex.org/keywords/stateful-firewall","display_name":"Stateful firewall","score":0.4780367314815521},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.45489779114723206},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.4337727427482605},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.429476797580719},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4269348978996277},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4230136275291443},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4215081036090851},{"id":"https://openalex.org/keywords/repeater","display_name":"Repeater (horology)","score":0.4129166603088379},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30557936429977417},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.25316834449768066},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.24897527694702148},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.2476416826248169},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1930769383907318},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1231050193309784}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6876364946365356},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.6595445871353149},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.5671924948692322},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5475167632102966},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.52838134765625},{"id":"https://openalex.org/C22927095","wikidata":"https://www.wikidata.org/wiki/Q1784206","display_name":"Stateful firewall","level":3,"score":0.4780367314815521},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.45489779114723206},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.4337727427482605},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.429476797580719},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4269348978996277},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4230136275291443},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4215081036090851},{"id":"https://openalex.org/C195545963","wikidata":"https://www.wikidata.org/wiki/Q1469803","display_name":"Repeater (horology)","level":3,"score":0.4129166603088379},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30557936429977417},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.25316834449768066},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.24897527694702148},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.2476416826248169},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1930769383907318},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1231050193309784},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1464971","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464971","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5799999833106995}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W116796504","https://openalex.org/W1511874886","https://openalex.org/W1891207585","https://openalex.org/W1999823427","https://openalex.org/W2097720613","https://openalex.org/W2113676942","https://openalex.org/W2119103834","https://openalex.org/W2131308327","https://openalex.org/W2133902254","https://openalex.org/W2147291108","https://openalex.org/W2159448561","https://openalex.org/W2159910740","https://openalex.org/W2160010046","https://openalex.org/W2160642395","https://openalex.org/W2161331676","https://openalex.org/W2171450866","https://openalex.org/W2300312103","https://openalex.org/W4246334093","https://openalex.org/W6604766017","https://openalex.org/W6681787770"],"related_works":["https://openalex.org/W2052455055","https://openalex.org/W1506442459","https://openalex.org/W2001020839","https://openalex.org/W4386968318","https://openalex.org/W331180034","https://openalex.org/W2090237663","https://openalex.org/W1487986186","https://openalex.org/W2224788396","https://openalex.org/W2174922170","https://openalex.org/W2169622190"],"abstract_inverted_index":{"Interconnect":[0],"delays":[1],"are":[2],"increasingly":[3],"becoming":[4],"the":[5,12,97],"dominant":[6],"source":[7],"of":[8,17,59,88,112],"performance":[9],"degradation":[10],"in":[11,90,115],"nanometer":[13],"regime,":[14],"largely":[15],"because":[16],"disturbances":[18],"that":[19,104],"result":[20],"from":[21],"parasitic":[22],"effects.":[23],"On":[24],"chip":[25],"communication":[26,56],"now":[27],"requires":[28],"multiple":[29,91],"clock":[30,93],"cycles":[31],"for":[32,73,86],"signal":[33],"propagation":[34],"between":[35,57],"communicating":[36],"modules/components.":[37],"Repeater":[38],"insertion":[39],"is":[40,82],"widely":[41],"used":[42],"to":[43,54],"improve":[44],"global":[45],"interconnect":[46],"delays.":[47],"We":[48,95],"propose":[49],"having":[50],"distributed":[51],"first-in-first-out":[52],"buffers":[53],"facilitate":[55],"components/modules":[58],"highly":[60],"integrated":[61],"systems,":[62],"such":[63],"as":[64],"system-on-chip.":[65],"This":[66],"stateful":[67],"scheme":[68],"has":[69],"very":[70],"good":[71],"tolerance":[72],"voltage":[74],"and":[75,84,99],"temperature":[76],"variations.":[77],"The":[78],"buffer":[79,98],"control":[80,102],"circuitry":[81],"self-timed":[83],"allows":[85],"ease":[87],"interfacing":[89],"domain":[92],"designs.":[94],"present":[96],"its":[100],"associated":[101],"circuits":[103],"allow":[105],"data":[106],"transfers":[107],"at":[108],"a":[109,116],"maximum":[110],"frequency":[111],"1.67":[113],"GHz":[114],"0.25":[117],"/spl":[118],"mu/m":[119],"technology.":[120]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
