{"id":"https://openalex.org/W2124766354","doi":"https://doi.org/10.1109/iscas.2005.1464968","title":"Glitch-free Discretely Programmable Clock Generation on chip","display_name":"Glitch-free Discretely Programmable Clock Generation on chip","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2124766354","doi":"https://doi.org/10.1109/iscas.2005.1464968","mag":"2124766354"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1464968","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464968","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://research.tue.nl/en/publications/8c2f6d97-22a3-4b9b-9145-6e3ef59f49a8","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061465128","display_name":"Maurice Meijer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"M. Meijer","raw_affiliation_strings":["Philips Research Laboratories, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"Philips Research Laboratories, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I4210122849"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085927985","display_name":"F. Pessolano","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"F. Pessolano","raw_affiliation_strings":["Philips Semiconductors, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"Philips Semiconductors, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I4210122849"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050945839","display_name":"Jos\u00e9 Pineda de Gyvez","orcid":"https://orcid.org/0000-0002-0723-7065"},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"J. Pineda de Gyvez","raw_affiliation_strings":["Philips Research Laboratories, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"Philips Research Laboratories, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I4210122849"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5061465128"],"corresponding_institution_ids":["https://openalex.org/I4210122849"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.18930697,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1839","last_page":"1842"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/glitch","display_name":"Glitch","score":0.9041881561279297},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7970302700996399},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6901052594184875},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6448169946670532},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6418249607086182},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6168792247772217},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5266934633255005},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.5232883095741272},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.49737241864204407},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.49460217356681824},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.467315137386322},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44229844212532043},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.41990065574645996},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41550368070602417},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4060328006744385},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.39559105038642883},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39492154121398926},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.31575557589530945},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16401344537734985},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.12459218502044678},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09508925676345825},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.08069610595703125}],"concepts":[{"id":"https://openalex.org/C191287063","wikidata":"https://www.wikidata.org/wiki/Q543281","display_name":"Glitch","level":3,"score":0.9041881561279297},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7970302700996399},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6901052594184875},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6448169946670532},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6418249607086182},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6168792247772217},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5266934633255005},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.5232883095741272},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.49737241864204407},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.49460217356681824},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.467315137386322},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44229844212532043},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.41990065574645996},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41550368070602417},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4060328006744385},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.39559105038642883},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39492154121398926},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.31575557589530945},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16401344537734985},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.12459218502044678},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09508925676345825},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.08069610595703125},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas.2005.1464968","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464968","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.tue.nl:openaire/8c2f6d97-22a3-4b9b-9145-6e3ef59f49a8","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/8c2f6d97-22a3-4b9b-9145-6e3ef59f49a8","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Meijer, M, Pessolano, F & Pineda de Gyvez, J 2005, Glitch-free discretely programmable clock generation on chip. in IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, May 23-26 Kobe, Japan. Institute of Electrical and Electronics Engineers, Piscataway, pp. 1839-1842. https://doi.org/10.1109/ISCAS.2005.1464968","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:tue:oai:pure.tue.nl:publications/8c2f6d97-22a3-4b9b-9145-6e3ef59f49a8","is_oa":true,"landing_page_url":"https://research.tue.nl/nl/publications/8c2f6d97-22a3-4b9b-9145-6e3ef59f49a8","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, May 23-26 Kobe, Japan, 1839 - 1842","raw_type":"info:eu-repo/semantics/conferencepaper"}],"best_oa_location":{"id":"pmh:oai:pure.tue.nl:openaire/8c2f6d97-22a3-4b9b-9145-6e3ef59f49a8","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/8c2f6d97-22a3-4b9b-9145-6e3ef59f49a8","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Meijer, M, Pessolano, F & Pineda de Gyvez, J 2005, Glitch-free discretely programmable clock generation on chip. in IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, May 23-26 Kobe, Japan. Institute of Electrical and Electronics Engineers, Piscataway, pp. 1839-1842. https://doi.org/10.1109/ISCAS.2005.1464968","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5199999809265137}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1609287256","https://openalex.org/W2119986070","https://openalex.org/W2131308327","https://openalex.org/W2168221955","https://openalex.org/W4246334093","https://openalex.org/W6636576922","https://openalex.org/W6684383791"],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W4386968318","https://openalex.org/W2337711143","https://openalex.org/W3006003651","https://openalex.org/W2137310043","https://openalex.org/W2294981364","https://openalex.org/W2040807843","https://openalex.org/W2088914741","https://openalex.org/W2286776167","https://openalex.org/W2495024767"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"describe":[4],"a":[5,8,21,45,63],"solution":[6],"for":[7,44,62],"glitch-free":[9],"discretely":[10],"programmable":[11],"clock":[12,29,32,47],"generation":[13],"unit":[14],"(DPGC).":[15],"The":[16],"scheme":[17,24,39,77],"is":[18,52],"compatible":[19],"with":[20,78],"GALS":[22],"communication":[23],"in":[25],"the":[26,37,49,73,76],"sense":[27],"that":[28],"gating":[30],"and":[31],"pausing":[33],"are":[34],"possible.":[35],"Besides,":[36],"proposed":[38],"does":[40],"not":[41],"require":[42],"waiting":[43],"new":[46],"as":[48,54],"frequency":[50],"change":[51],"seen":[53],"almost":[55],"instantaneously.":[56],"A":[57],"prototype":[58],"has":[59],"been":[60],"designed":[61],"0.13/spl":[64],"mu/m":[65],"triple-well":[66],"CMOS":[67],"process":[68],"technology":[69],"to":[70,80],"also":[71],"study":[72],"properties":[74],"of":[75],"respect":[79],"voltage":[81],"scaling.":[82]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}