{"id":"https://openalex.org/W2164560364","doi":"https://doi.org/10.1109/iscas.2005.1464925","title":"Enhancing the Efficiency of Cluster Voltage Scaling Technique for Low-power Application","display_name":"Enhancing the Efficiency of Cluster Voltage Scaling Technique for Low-power Application","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2164560364","doi":"https://doi.org/10.1109/iscas.2005.1464925","mag":"2164560364"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1464925","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464925","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029728957","display_name":"Behnam Amelifard","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]},{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR","US"],"is_corresponding":false,"raw_author_name":"B. Amelifard","raw_affiliation_strings":["Low-Power High-Performance Nanosystems Laboratory, University of Tehran, Tehran, Iran","System Power Optimization and Regulation Technology Lab, University of Southern California, Los Angeles, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Low-Power High-Performance Nanosystems Laboratory, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"System Power Optimization and Regulation Technology Lab, University of Southern California, Los Angeles, CA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074063358","display_name":"Ali Afzali\u2010Kusha","orcid":"https://orcid.org/0000-0001-8614-2007"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"A. Afzali-Kusha","raw_affiliation_strings":["Low-Power High-Performance Nanosystems Laboratory, University of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Low-Power High-Performance Nanosystems Laboratory, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035297802","display_name":"Ahmad Khademzadeh","orcid":"https://orcid.org/0000-0001-9352-7466"},"institutions":[{"id":"https://openalex.org/I4210102178","display_name":"ICT Research Institute","ror":"https://ror.org/01a3g2z22","country_code":"IR","type":"facility","lineage":["https://openalex.org/I4210102178"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"A. Khademzadeh","raw_affiliation_strings":["Iran Telecommunication Research Center"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Iran Telecommunication Research Center","institution_ids":["https://openalex.org/I4210102178"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3634,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.68908811,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1666","last_page":"1669"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5844963192939758},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.5811064839363098},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5751084685325623},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5750910043716431},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.5593370795249939},{"id":"https://openalex.org/keywords/dynamic-voltage-scaling","display_name":"Dynamic voltage scaling","score":0.5587067604064941},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.5393886566162109},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5337783694267273},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5203449130058289},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5170732140541077},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4772788882255554},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.46562713384628296},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.46234244108200073},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.44188234210014343},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4168807864189148},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2720103859901428},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11664238572120667},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10510972142219543}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5844963192939758},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.5811064839363098},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5751084685325623},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5750910043716431},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.5593370795249939},{"id":"https://openalex.org/C2776047111","wikidata":"https://www.wikidata.org/wiki/Q632037","display_name":"Dynamic voltage scaling","level":3,"score":0.5587067604064941},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.5393886566162109},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5337783694267273},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5203449130058289},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5170732140541077},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4772788882255554},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.46562713384628296},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.46234244108200073},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.44188234210014343},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4168807864189148},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2720103859901428},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11664238572120667},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10510972142219543},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2005.1464925","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464925","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.79.7801","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.79.7801","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://atrak.usc.edu/~behnam/papers/iscas05-1.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1507504962","https://openalex.org/W1511688816","https://openalex.org/W1586205518","https://openalex.org/W1996623312","https://openalex.org/W1997742530","https://openalex.org/W2057443927","https://openalex.org/W2080686598","https://openalex.org/W2107445769","https://openalex.org/W2121190917","https://openalex.org/W2157024459","https://openalex.org/W2169278276","https://openalex.org/W3103339143","https://openalex.org/W6630623413"],"related_works":["https://openalex.org/W575537888","https://openalex.org/W2014213913","https://openalex.org/W2512653194","https://openalex.org/W1948744433","https://openalex.org/W2183734887","https://openalex.org/W2114346412","https://openalex.org/W4386952610","https://openalex.org/W38731190","https://openalex.org/W1491122910","https://openalex.org/W3215411922"],"abstract_inverted_index":{"In":[0,44],"this":[1],"paper,":[2],"a":[3,34],"scheme":[4],"for":[5,14],"power":[6,26,37,58,89],"reduction":[7,27,84],"based":[8],"on":[9,82],"cluster":[10],"voltage":[11],"scaling":[12],"(CVS)":[13],"gate-level":[15],"design":[16],"of":[17,29,48,66,76,85],"the":[18,25,30,42,46,57,70,83],"VLSI":[19],"circuits":[20],"is":[21,39],"presented.":[22],"To":[23],"increase":[24],"efficiency":[28],"previous":[31,71],"CVS":[32,72,77],"techniques,":[33],"new":[35],"low":[36],"level-shifter":[38],"utilized":[40],"in":[41],"circuit.":[43],"addition,":[45],"concept":[47],"transistor":[49],"ordering":[50],"has":[51],"been":[52],"used":[53],"to":[54,69],"further":[55],"reduce":[56],"consumption.":[59],"This":[60],"technique":[61],"shows":[62],"an":[63],"average":[64],"improvement":[65],"7%":[67],"compared":[68],"circuits.":[73],"The":[74],"impact":[75],"and":[78,87],"its":[79],"modified":[80],"version":[81],"short-circuit":[86],"leakage":[88],"are":[90],"also":[91],"discussed.":[92]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}