{"id":"https://openalex.org/W2119221715","doi":"https://doi.org/10.1109/iscas.2005.1464814","title":"A Low Power FPGA Routing Architecture","display_name":"A Low Power FPGA Routing Architecture","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2119221715","doi":"https://doi.org/10.1109/iscas.2005.1464814","mag":"2119221715"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1464814","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464814","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110207334","display_name":"Sorbojit Mondal","orcid":"https://orcid.org/0009-0005-4416-0924"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S. Mondal","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, USA","Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111716641","display_name":"Seda \u00d6\u01e7renci Memik","orcid":null},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.O. Memik","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, USA","Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5110207334"],"corresponding_institution_ids":["https://openalex.org/I111979921"],"apc_list":null,"apc_paid":null,"fwci":1.4227,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.83084154,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1222","last_page":"1225"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7965896129608154},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6477782130241394},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6112414598464966},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5852404832839966},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5768704414367676},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5183371305465698},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5102131366729736},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4705524742603302},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.4582902193069458},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4230389893054962},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3400028944015503},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3210088014602661},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.174216628074646},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.1564207375049591}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7965896129608154},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6477782130241394},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6112414598464966},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5852404832839966},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5768704414367676},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5183371305465698},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5102131366729736},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4705524742603302},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.4582902193069458},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4230389893054962},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3400028944015503},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3210088014602661},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.174216628074646},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.1564207375049591},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1464814","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464814","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.75}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W141741427","https://openalex.org/W1523051745","https://openalex.org/W1557877906","https://openalex.org/W2039097694","https://openalex.org/W2109846948","https://openalex.org/W2121190917","https://openalex.org/W2124021899","https://openalex.org/W2124146551","https://openalex.org/W2132225593","https://openalex.org/W2137978438","https://openalex.org/W2151731855","https://openalex.org/W2159142998","https://openalex.org/W2170510975","https://openalex.org/W4241560890","https://openalex.org/W6605818641","https://openalex.org/W6642590662","https://openalex.org/W6682337876"],"related_works":["https://openalex.org/W2197466303","https://openalex.org/W2534453537","https://openalex.org/W2151236218","https://openalex.org/W4234601000","https://openalex.org/W1512285683","https://openalex.org/W2187918628","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2170504327","https://openalex.org/W2526300902"],"abstract_inverted_index":{"Significant":[0],"headway":[1],"has":[2],"been":[3],"made":[4],"in":[5,12,93],"logic":[6],"density":[7],"and":[8,66,78,104],"performance":[9],"of":[10,18,49,56,72,87],"FPGAs":[11],"the":[13,23,45,50,57,70],"past":[14],"decade.":[15],"Power":[16],"efficiency":[17],"FPGA":[19],"architectures":[20],"is":[21,42,97],"arguably":[22],"next":[24],"most":[25],"important":[26],"criterion":[27],"that":[28,83],"needs":[29],"improvement.":[30],"In":[31],"this":[32,73],"paper,":[33],"we":[34],"propose":[35],"an":[36,54,84],"interconnect":[37,47,64,95],"architecture,":[38],"where":[39],"voltage":[40],"scaling":[41],"applied":[43],"within":[44],"programmable":[46],"structure":[48],"FPGA.":[51],"We":[52],"present":[53,67],"evaluation":[55],"overhead":[58,107],"associated":[59],"with":[60,99],"dual-V/sub":[61],"dd/-dual-V/sub":[62],"t/":[63],"architecture":[65,75],"results":[68],"on":[69,76,108],"impact":[71],"routing":[74],"area":[77,106],"delay.":[79],"Our":[80],"experiments":[81],"reveal":[82],"average":[85],"reduction":[86],"23.45%":[88],"(as":[89],"high":[90],"as":[91],"47%)":[92],"total":[94],"power":[96],"achievable":[98],"11.75%":[100],"worst-case":[101],"delay":[102],"penalty":[103],"6%":[105],"average.":[109]},"counts_by_year":[{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}