{"id":"https://openalex.org/W2118118665","doi":"https://doi.org/10.1109/iscas.2005.1464779","title":"A Linear Model for High-Level Delay Estimation in VDSM On-Chip Interconnects","display_name":"A Linear Model for High-Level Delay Estimation in VDSM On-Chip Interconnects","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2118118665","doi":"https://doi.org/10.1109/iscas.2005.1464779","mag":"2118118665"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1464779","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464779","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071163639","display_name":"Tudor Murgan","orcid":null},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"T. Murgan","raw_affiliation_strings":["Inst. of Microelectronic Systems, Darmstadt Univ. of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Inst. of Microelectronic Systems, Darmstadt Univ. of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050344559","display_name":"Alberto Garc\u00eda-Ortiz","orcid":"https://orcid.org/0000-0002-6461-3864"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"A.G. Ortiz","raw_affiliation_strings":["Inst. of Microelectronic Systems, Darmstadt Univ. of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Inst. of Microelectronic Systems, Darmstadt Univ. of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071942429","display_name":"M. Petrov","orcid":"https://orcid.org/0000-0002-2711-8469"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Petrov","raw_affiliation_strings":["Inst. of Microelectronic Systems, Darmstadt Univ. of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Inst. of Microelectronic Systems, Darmstadt Univ. of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002162776","display_name":"Manfred Glesner","orcid":null},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Glesner","raw_affiliation_strings":["Inst. of Microelectronic Systems, Darmstadt Univ. of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Inst. of Microelectronic Systems, Darmstadt Univ. of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5071163639"],"corresponding_institution_ids":["https://openalex.org/I31512782"],"apc_list":null,"apc_paid":null,"fwci":0.7246,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.75064541,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1078","last_page":"1081"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.7262015342712402},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6463350653648376},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5358976125717163},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5223866105079651},{"id":"https://openalex.org/keywords/linear-model","display_name":"Linear model","score":0.4862583875656128},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4242766499519348},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3787990212440491},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20413312315940857},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14148414134979248},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10978320240974426}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.7262015342712402},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6463350653648376},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5358976125717163},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5223866105079651},{"id":"https://openalex.org/C163175372","wikidata":"https://www.wikidata.org/wiki/Q3339222","display_name":"Linear model","level":2,"score":0.4862583875656128},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4242766499519348},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3787990212440491},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20413312315940857},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14148414134979248},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10978320240974426},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2005.1464779","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464779","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:tubiblio.ulb.tu-darmstadt.de:27156","is_oa":false,"landing_page_url":"http://tubiblio.ulb.tu-darmstadt.de/view/person/Murgan=3ATudor=3A=3A.html>","pdf_url":null,"source":{"id":"https://openalex.org/S4377196390","display_name":"TUbilio (Technical University of Darmstadt)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I31512782","host_organization_name":"Technische Universit\u00e4t Darmstadt","host_organization_lineage":["https://openalex.org/I31512782"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"NonPeerReviewed"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W619070166","https://openalex.org/W1545862813","https://openalex.org/W1559479636","https://openalex.org/W2031538835","https://openalex.org/W2063253975","https://openalex.org/W2066910438","https://openalex.org/W2072373780","https://openalex.org/W2075891646","https://openalex.org/W2097056724","https://openalex.org/W2107915259","https://openalex.org/W2157089032","https://openalex.org/W2157763958","https://openalex.org/W2167478831","https://openalex.org/W3127394485","https://openalex.org/W4237819149","https://openalex.org/W6674274919"],"related_works":["https://openalex.org/W2204879205","https://openalex.org/W2610849239","https://openalex.org/W2041608016","https://openalex.org/W2088504085","https://openalex.org/W2037642033","https://openalex.org/W2360388749","https://openalex.org/W1674491244","https://openalex.org/W2065289416","https://openalex.org/W2017236304","https://openalex.org/W2136854845"],"abstract_inverted_index":{"This":[0],"work":[1],"introduces":[2],"a":[3,31],"linear":[4,32],"model":[5,25,95],"for":[6,55,66,78],"high-level":[7,82],"prediction":[8],"of":[9,34,59,84,93,101],"delay":[10,29,47,89],"in":[11,48,71],"capacitively":[12,50],"and":[13,51,63,108],"inductively":[14,52],"coupled":[15,53],"very":[16],"deep":[17],"sub-micron":[18],"(VDSM)":[19],"on-chip":[20],"interconnects.":[21],"The":[22,91],"proposed":[23],"estimation":[24],"approximates":[26],"the":[27,35,46,56,60,67,94],"signal":[28],"as":[30,70],"combination":[33],"contributions":[36],"induced":[37],"by":[38,99],"each":[39],"other":[40],"aggressor":[41],"line.":[42],"It":[43],"accurately":[44],"predicts":[45],"both":[49],"lines":[54],"complete":[57],"set":[58],"switching":[61],"patterns,":[62],"not":[64],"only":[65],"worst":[68],"case,":[69],"previous":[72],"works.":[73],"Therefore,":[74],"it":[75],"is":[76],"suitable":[77],"fast":[79],"yet":[80],"efficient":[81],"analysis":[83],"bus":[85],"encoding":[86],"schemes":[87],"envisaging":[88],"minimisation.":[90],"accuracy":[92],"has":[96],"been":[97],"assessed":[98],"means":[100],"extensive":[102],"experiments":[103],"using":[104],"3D":[105],"field":[106],"solvers":[107],"SPICE":[109],"simulations.":[110]},"counts_by_year":[],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}
