{"id":"https://openalex.org/W2150834427","doi":"https://doi.org/10.1109/iscas.2005.1464776","title":"A Novel CMOS Logic Style with Data Independent Power Consumption","display_name":"A Novel CMOS Logic Style with Data Independent Power Consumption","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2150834427","doi":"https://doi.org/10.1109/iscas.2005.1464776","mag":"2150834427"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1464776","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464776","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054583230","display_name":"Manfred Aigner","orcid":"https://orcid.org/0000-0001-8723-4966"},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"M. Aigner","raw_affiliation_strings":["Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Graz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015437576","display_name":"Stefan Mangard","orcid":"https://orcid.org/0000-0001-9650-8041"},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"S. Mangard","raw_affiliation_strings":["Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Graz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066580663","display_name":"Renato Menicocci","orcid":null},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Menicocci","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma La Sapienza, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067054447","display_name":"Mauro Olivieri","orcid":"https://orcid.org/0000-0002-0214-9904"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Olivieri","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma La Sapienza, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010336494","display_name":"Giuseppe Scotti","orcid":"https://orcid.org/0000-0002-5650-8212"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Scotti","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma La Sapienza, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068452963","display_name":"Alessandro Trifiletti","orcid":"https://orcid.org/0000-0001-6231-4273"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Trifiletti","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma La Sapienza, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1066","last_page":"1069"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7766952514648438},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.722619891166687},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6743156909942627},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6350818872451782},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6331664323806763},{"id":"https://openalex.org/keywords/pull-up-resistor","display_name":"Pull-up resistor","score":0.6235109567642212},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5582637190818787},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.5539382100105286},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.535105288028717},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4891052842140198},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4396456182003021},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4354490041732788},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.4338369369506836},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.4207797050476074},{"id":"https://openalex.org/keywords/dynamic-logic","display_name":"Dynamic logic (digital electronics)","score":0.41160067915916443},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4068000912666321},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32370656728744507},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.23872780799865723},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2306230068206787},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.21360361576080322},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.15978968143463135},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.15654399991035461},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.12083184719085693}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7766952514648438},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.722619891166687},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6743156909942627},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6350818872451782},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6331664323806763},{"id":"https://openalex.org/C61818909","wikidata":"https://www.wikidata.org/wiki/Q1987617","display_name":"Pull-up resistor","level":5,"score":0.6235109567642212},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5582637190818787},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.5539382100105286},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.535105288028717},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4891052842140198},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4396456182003021},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4354490041732788},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.4338369369506836},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.4207797050476074},{"id":"https://openalex.org/C2777796570","wikidata":"https://www.wikidata.org/wiki/Q2351326","display_name":"Dynamic logic (digital electronics)","level":4,"score":0.41160067915916443},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4068000912666321},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32370656728744507},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.23872780799865723},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2306230068206787},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.21360361576080322},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15978968143463135},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.15654399991035461},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.12083184719085693},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2005.1464776","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464776","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.uniroma1.it:11573/471769","is_oa":false,"landing_page_url":"http://hdl.handle.net/11573/471769","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1503689022","https://openalex.org/W1560093457","https://openalex.org/W1563937974","https://openalex.org/W1602420333","https://openalex.org/W2026871322","https://openalex.org/W2105114022","https://openalex.org/W2154909745","https://openalex.org/W3043704532","https://openalex.org/W4285719527","https://openalex.org/W6635937959"],"related_works":["https://openalex.org/W2580743037","https://openalex.org/W2082591327","https://openalex.org/W2155174752","https://openalex.org/W1996543053","https://openalex.org/W1900707063","https://openalex.org/W2247471973","https://openalex.org/W1994690319","https://openalex.org/W4324145463","https://openalex.org/W1601832081","https://openalex.org/W4324145462"],"abstract_inverted_index":{"We":[0,43],"propose":[1],"a":[2,28,46,52],"novel":[3],"dynamic":[4],"CMOS":[5,60],"logic":[6,16,36,49],"style":[7],"to":[8,57],"protect":[9],"security":[10],"devices":[11],"against":[12],"power":[13,29,69,75],"attacks.":[14],"The":[15],"is":[17],"based":[18],"on":[19],"signals":[20],"with":[21,27],"3":[22],"possible":[23],"states":[24],"and":[25,38,51,54,68,73],"operates":[26],"consumption":[30],"ideally":[31],"independent":[32],"of":[33,41,48,64],"both":[34],"the":[35,39],"values":[37],"sequence":[40],"data.":[42],"have":[44],"designed":[45],"set":[47],"gates":[50],"flip-flop":[53],"compared":[55],"those":[56],"static":[58],"complementary":[59],"implementations":[61],"in":[62],"terms":[63],"correlation":[65],"between":[66],"data":[67],"consumption,":[70],"speed,":[71],"area,":[72],"total":[74],"dissipation.":[76]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}