{"id":"https://openalex.org/W2139550811","doi":"https://doi.org/10.1109/iscas.2005.1464773","title":"A 12.5 Gbps CMOS Input Sampler for Serial Link Receiver Front End","display_name":"A 12.5 Gbps CMOS Input Sampler for Serial Link Receiver Front End","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2139550811","doi":"https://doi.org/10.1109/iscas.2005.1464773","mag":"2139550811"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1464773","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464773","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061859062","display_name":"Shyh\u2010Jye Jou","orcid":"https://orcid.org/0000-0002-8821-3486"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Shyh-Jye Jou","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102760864","display_name":"Chih-Hsien Lin","orcid":"https://orcid.org/0000-0002-6754-5131"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]},{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chih-Hsien Lin","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Chungli, Taiwan","National Yang Ming Chiao Tung University"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Chungli, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"National Yang Ming Chiao Tung University","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113682463","display_name":"Yen-I Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yen-I Wang","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Chungli, Taiwan","National Central University#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Chungli, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"National Central University#TAB#","institution_ids":["https://openalex.org/I22265921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5061859062"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1990774,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"31","issue":null,"first_page":"1055","last_page":"1058"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.8552341461181641},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7745890617370605},{"id":"https://openalex.org/keywords/oversampling","display_name":"Oversampling","score":0.7147167325019836},{"id":"https://openalex.org/keywords/gigabit","display_name":"Gigabit","score":0.6105988025665283},{"id":"https://openalex.org/keywords/front-and-back-ends","display_name":"Front and back ends","score":0.5956482887268066},{"id":"https://openalex.org/keywords/serial-communication","display_name":"Serial communication","score":0.5634551048278809},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5298188924789429},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.5090303421020508},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.49607357382774353},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.49009525775909424},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4620389938354492},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44049137830734253},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.43077513575553894},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.32384562492370605},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25371652841567993},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2306261956691742}],"concepts":[{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.8552341461181641},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7745890617370605},{"id":"https://openalex.org/C197323446","wikidata":"https://www.wikidata.org/wiki/Q331222","display_name":"Oversampling","level":3,"score":0.7147167325019836},{"id":"https://openalex.org/C21922175","wikidata":"https://www.wikidata.org/wiki/Q3105497","display_name":"Gigabit","level":2,"score":0.6105988025665283},{"id":"https://openalex.org/C53016008","wikidata":"https://www.wikidata.org/wiki/Q620167","display_name":"Front and back ends","level":2,"score":0.5956482887268066},{"id":"https://openalex.org/C51707140","wikidata":"https://www.wikidata.org/wiki/Q518280","display_name":"Serial communication","level":2,"score":0.5634551048278809},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5298188924789429},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.5090303421020508},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49607357382774353},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.49009525775909424},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4620389938354492},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44049137830734253},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43077513575553894},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.32384562492370605},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25371652841567993},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2306261956691742},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1464773","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464773","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1570637267","https://openalex.org/W1988315752","https://openalex.org/W2042380162","https://openalex.org/W2105696031","https://openalex.org/W2116902131","https://openalex.org/W2123716779","https://openalex.org/W3142431408","https://openalex.org/W6633957760"],"related_works":["https://openalex.org/W2766503024","https://openalex.org/W2781247653","https://openalex.org/W4206637278","https://openalex.org/W4386005305","https://openalex.org/W3082051559","https://openalex.org/W4386214543","https://openalex.org/W1969988626","https://openalex.org/W1682621979","https://openalex.org/W2141301039","https://openalex.org/W3173198409"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,10,21,23,27,31,65,98],"high-speed":[4],"CMOS":[5],"input":[6,17,52,60,85],"sampler":[7,18],"used":[8,35],"for":[9,36,46],"serial":[11],"link":[12],"receiver":[13,56],"front":[14,57],"end.":[15,58],"The":[16,79],"consists":[19],"of":[20,74,88,94,101],"comparator,":[22],"SR":[24],"latch":[25],"and":[26,40],"D":[28],"flip-flop.":[29],"Because":[30],"parallel":[32],"architecture":[33],"is":[34,44],"the":[37,55],"1:8":[38],"demultiplexing":[39],"3/spl":[41],"times/":[42],"oversampling":[43],"utilized":[45],"data":[47,86],"recovery,":[48],"there":[49],"are":[50,62],"24":[51],"samplers":[53,61],"in":[54,64],"These":[59],"implemented":[63],"TSMC":[66],"0.18":[67],"/spl":[68,76],"mu/m":[69],"1P6M":[70],"process":[71],"with":[72,91],"area":[73],"252*162":[75],"mu/m/sup":[77],"2/.":[78],"circuits":[80],"can":[81],"operate":[82],"at":[83],"maximum":[84],"rate":[87],"12.7":[89],"Gbit/s":[90],"differential":[92],"signal":[93],"300":[95],"mV":[96],"using":[97],"supply":[99],"voltage":[100],"1.8V.":[102]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
