{"id":"https://openalex.org/W2170095710","doi":"https://doi.org/10.1109/iscas.2005.1464771","title":"Efficient Implementation of Trace-back Unit in a Reconfigurable Viterbi Decoder Fabric","display_name":"Efficient Implementation of Trace-back Unit in a Reconfigurable Viterbi Decoder Fabric","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2170095710","doi":"https://doi.org/10.1109/iscas.2005.1464771","mag":"2170095710"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1464771","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464771","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010796482","display_name":"Cheng Zhan","orcid":"https://orcid.org/0000-0002-0971-6748"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Cheng Zhan","raw_affiliation_strings":["School of Electronics and Engineering, University of Edinburgh, Edinburgh, UK"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Engineering, University of Edinburgh, Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035104014","display_name":"S. Khawam","orcid":null},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"S. Khawam","raw_affiliation_strings":["School of Electronics and Engineering, University of Edinburgh, Edinburgh, UK"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Engineering, University of Edinburgh, Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022272531","display_name":"Tughrul Arslan","orcid":"https://orcid.org/0000-0001-8176-5803"},"institutions":[{"id":"https://openalex.org/I2799593479","display_name":"Education Scotland","ror":"https://ror.org/05yapj268","country_code":"GB","type":"government","lineage":["https://openalex.org/I2799593479","https://openalex.org/I2801269068"]},{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"T. Arslan","raw_affiliation_strings":["School of Electronics and Engineering, University of Edinburgh, Edinburgh, UK","The Alba Centre, Institute for System Level Integration, Livingston, UK"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Engineering, University of Edinburgh, Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]},{"raw_affiliation_string":"The Alba Centre, Institute for System Level Integration, Livingston, UK","institution_ids":["https://openalex.org/I2799593479"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110201534","display_name":"Iain Lindsay","orcid":null},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"I. Lindsay","raw_affiliation_strings":["School of Electronics and Engineering, University of Edinburgh, Edinburgh, UK"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Engineering, University of Edinburgh, Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5010796482"],"corresponding_institution_ids":["https://openalex.org/I98677209"],"apc_list":null,"apc_paid":null,"fwci":0.3628,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.6903423,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1048","last_page":"1050"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/viterbi-decoder","display_name":"Viterbi decoder","score":0.8766449093818665},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7544467449188232},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7133921980857849},{"id":"https://openalex.org/keywords/viterbi-algorithm","display_name":"Viterbi algorithm","score":0.660528302192688},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5426498055458069},{"id":"https://openalex.org/keywords/ranging","display_name":"Ranging","score":0.5350130200386047},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5083364844322205},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.504874050617218},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47485044598579407},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.4722651243209839},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.46410831809043884},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.44234713912010193},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.4264300465583801},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4197898805141449},{"id":"https://openalex.org/keywords/soft-output-viterbi-algorithm","display_name":"Soft output Viterbi algorithm","score":0.4187498390674591},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.41177552938461304},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3288886547088623},{"id":"https://openalex.org/keywords/sequential-decoding","display_name":"Sequential decoding","score":0.12159392237663269},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.1071506142616272},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09864723682403564},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06914836168289185}],"concepts":[{"id":"https://openalex.org/C117379686","wikidata":"https://www.wikidata.org/wiki/Q6996459","display_name":"Viterbi decoder","level":3,"score":0.8766449093818665},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7544467449188232},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7133921980857849},{"id":"https://openalex.org/C60582962","wikidata":"https://www.wikidata.org/wiki/Q83886","display_name":"Viterbi algorithm","level":3,"score":0.660528302192688},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5426498055458069},{"id":"https://openalex.org/C115051666","wikidata":"https://www.wikidata.org/wiki/Q6522493","display_name":"Ranging","level":2,"score":0.5350130200386047},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5083364844322205},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.504874050617218},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47485044598579407},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.4722651243209839},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.46410831809043884},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.44234713912010193},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.4264300465583801},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4197898805141449},{"id":"https://openalex.org/C130319729","wikidata":"https://www.wikidata.org/wiki/Q83886","display_name":"Soft output Viterbi algorithm","level":5,"score":0.4187498390674591},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.41177552938461304},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3288886547088623},{"id":"https://openalex.org/C193969084","wikidata":"https://www.wikidata.org/wiki/Q7452500","display_name":"Sequential decoding","level":4,"score":0.12159392237663269},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.1071506142616272},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09864723682403564},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06914836168289185},{"id":"https://openalex.org/C157125643","wikidata":"https://www.wikidata.org/wiki/Q884707","display_name":"Block code","level":3,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2005.1464771","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464771","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.501.3403","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.501.3403","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.see.ed.ac.uk/~slig/papers/cheng.iscas05.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8399999737739563,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1991133427","https://openalex.org/W2129633426","https://openalex.org/W3128611524"],"related_works":["https://openalex.org/W2143297499","https://openalex.org/W2146383045","https://openalex.org/W2790444905","https://openalex.org/W3096277017","https://openalex.org/W4232476001","https://openalex.org/W2099620359","https://openalex.org/W2544568790","https://openalex.org/W3012243213","https://openalex.org/W2783469447","https://openalex.org/W2133857928"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,12,56,64],"reconfigurable":[4,19],"Viterbi":[5,23],"fabric":[6,20],"with":[7,25,55],"efficient":[8],"track-back":[9],"unit":[10],"in":[11,36],"system":[13],"on":[14],"chip":[15],"device.":[16],"The":[17],"proposed":[18,45],"can":[21],"support":[22],"implementations":[24],"constraint":[26],"lengths":[27],"ranging":[28],"from":[29],"3":[30],"to":[31],"9,":[32],"and":[33,51,63],"code":[34],"rates":[35],"the":[37,44],"range":[38],"1/2-1/3.":[39],"Our":[40],"results":[41],"illustrate":[42],"that":[43],"architecture":[46],"has":[47],"superior":[48],"power":[49],"consumption":[50],"throughput":[52],"characteristics":[53],"compared":[54],"generic":[57],"field":[58],"programmable":[59],"gate":[60],"array":[61],"(FPGA)":[62],"digital":[65],"signal":[66],"processor":[67],"(DSP),":[68],"respectively.":[69]},"counts_by_year":[{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}