{"id":"https://openalex.org/W2113324266","doi":"https://doi.org/10.1109/iscas.2005.1464593","title":"A Memory-Based Architecture for FPGA Implementations of Low-Density Parity-Check Convolutional Decoders","display_name":"A Memory-Based Architecture for FPGA Implementations of Low-Density Parity-Check Convolutional Decoders","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2113324266","doi":"https://doi.org/10.1109/iscas.2005.1464593","mag":"2113324266"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1464593","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464593","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057257463","display_name":"Stephen Bates","orcid":"https://orcid.org/0000-0002-9182-1167"},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"S. Bates","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada","[Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada","institution_ids":["https://openalex.org/I154425047"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada]","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031747007","display_name":"Gary L. Block","orcid":null},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"G. Block","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada","[Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada","institution_ids":["https://openalex.org/I154425047"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada]","institution_ids":["https://openalex.org/I154425047"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5057257463"],"corresponding_institution_ids":["https://openalex.org/I154425047"],"apc_list":null,"apc_paid":null,"fwci":4.1528,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.94715161,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"336","last_page":"339"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.9049839973449707},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.814949631690979},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7511794567108154},{"id":"https://openalex.org/keywords/convolutional-code","display_name":"Convolutional code","score":0.5810451507568359},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5490893125534058},{"id":"https://openalex.org/keywords/low-density-parity-check-code","display_name":"Low-density parity-check code","score":0.50107741355896},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.47082287073135376},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4583775997161865},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.43234822154045105},{"id":"https://openalex.org/keywords/soft-decision-decoder","display_name":"Soft-decision decoder","score":0.4305541515350342},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4267151355743408},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.4133046269416809},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40627986192703247},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33478525280952454},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1538471281528473},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14427220821380615}],"concepts":[{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.9049839973449707},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.814949631690979},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7511794567108154},{"id":"https://openalex.org/C157899210","wikidata":"https://www.wikidata.org/wiki/Q1395022","display_name":"Convolutional code","level":3,"score":0.5810451507568359},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5490893125534058},{"id":"https://openalex.org/C67692717","wikidata":"https://www.wikidata.org/wiki/Q187444","display_name":"Low-density parity-check code","level":3,"score":0.50107741355896},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.47082287073135376},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4583775997161865},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.43234822154045105},{"id":"https://openalex.org/C185588885","wikidata":"https://www.wikidata.org/wiki/Q7553811","display_name":"Soft-decision decoder","level":3,"score":0.4305541515350342},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4267151355743408},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.4133046269416809},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40627986192703247},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33478525280952454},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1538471281528473},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14427220821380615},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1464593","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1464593","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1553026542","https://openalex.org/W1578463314","https://openalex.org/W1991528082","https://openalex.org/W2107301532","https://openalex.org/W2121074861","https://openalex.org/W2137990712","https://openalex.org/W2538923492","https://openalex.org/W4213222928"],"related_works":["https://openalex.org/W1509155667","https://openalex.org/W2518118925","https://openalex.org/W2078980669","https://openalex.org/W3208151864","https://openalex.org/W1564576805","https://openalex.org/W2365203640","https://openalex.org/W2156108776","https://openalex.org/W2369207580","https://openalex.org/W4247279932","https://openalex.org/W4254372399"],"abstract_inverted_index":{"Low-density":[0],"parity-check":[1],"convolutional":[2],"codes":[3,34],"complement":[4],"their":[5],"popular":[6],"block-oriented":[7,120],"counterparts":[8],"and":[9,22,24,35,58,79,89],"may":[10],"be":[11],"more":[12],"suitable":[13],"in":[14],"certain":[15],"communication":[16],"applications.":[17],"These":[18],"include":[19],"streaming":[20],"voice":[21],"video":[23],"packet":[25],"switching":[26],"networks.":[27],"In":[28],"this":[29,71,115],"paper":[30],"we":[31],"introduce":[32],"these":[33],"propose":[36],"a":[37,68,90,112],"memory-based":[38],"decoder":[39,121],"architecture":[40,57,72],"that":[41,73],"is":[42],"well":[43],"suited":[44],"for":[45,77],"implementation":[46,114],"on":[47,106],"field-programmable":[48],"gate":[49],"arrays.":[50],"We":[51,65],"present":[52],"an":[53,101,107],"overview":[54],"of":[55,70,86,103],"the":[56],"demonstrate":[59],"its":[60],"efficiency":[61],"over":[62],"register-based":[63],"architectures.":[64],"then":[66],"discuss":[67],"realization":[69],"can":[74,80],"trade":[75],"performance":[76],"throughput":[78,88],"achieve":[81],"up":[82],"to":[83],"120":[84],"Mb/s":[85],"information":[87],"BER":[91],"as":[92,94],"low":[93],"2":[95],"/spl":[96],"times/":[97],"10/sup":[98],"-6/":[99],"at":[100],"Eb/Nq":[102],"3":[104],"dB":[105],"Altera":[108],"Stratix":[109],"FPGA.":[110],"For":[111],"first-generation":[113],"compares":[116],"favorable":[117],"with":[118],"current":[119],"implementations.":[122]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}