{"id":"https://openalex.org/W2154967995","doi":"https://doi.org/10.1109/iscas.2004.1328313","title":"A low-voltage low sensitivity sinusoidal VCO for DPLL realizations","display_name":"A low-voltage low sensitivity sinusoidal VCO for DPLL realizations","publication_year":2004,"publication_date":"2004-09-07","ids":{"openalex":"https://openalex.org/W2154967995","doi":"https://doi.org/10.1109/iscas.2004.1328313","mag":"2154967995"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2004.1328313","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2004.1328313","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11449/67875","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103533017","display_name":"Jader A. De Lima","orcid":null},"institutions":[{"id":"https://openalex.org/I879563668","display_name":"Universidade Estadual Paulista (Unesp)","ror":"https://ror.org/00987cb86","country_code":"BR","type":"education","lineage":["https://openalex.org/I879563668"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"J.A. De Lima","raw_affiliation_strings":["Laboratory of VLSI Design & Instrumentation, Electrical Engineering Department, Universidade Estadual Paulista (UNESP), Sao Paulo, Brazil"],"affiliations":[{"raw_affiliation_string":"Laboratory of VLSI Design & Instrumentation, Electrical Engineering Department, Universidade Estadual Paulista (UNESP), Sao Paulo, Brazil","institution_ids":["https://openalex.org/I879563668"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002224228","display_name":"Peterson R. Agostinho","orcid":null},"institutions":[{"id":"https://openalex.org/I879563668","display_name":"Universidade Estadual Paulista (Unesp)","ror":"https://ror.org/00987cb86","country_code":"BR","type":"education","lineage":["https://openalex.org/I879563668"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"P.R. Agostinho","raw_affiliation_strings":["Laboratory of VLSI Design & Instrumentation, Electrical Engineering Department, Universidade Estadual Paulista (UNESP), Sao Paulo, Brazil"],"affiliations":[{"raw_affiliation_string":"Laboratory of VLSI Design & Instrumentation, Electrical Engineering Department, Universidade Estadual Paulista (UNESP), Sao Paulo, Brazil","institution_ids":["https://openalex.org/I879563668"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5103533017"],"corresponding_institution_ids":["https://openalex.org/I879563668"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.17686366,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"48","issue":null,"first_page":"I","last_page":"789"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.9473560452461243},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.6089440584182739},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.5795714259147644},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5706673860549927},{"id":"https://openalex.org/keywords/oscillation","display_name":"Oscillation (cell signaling)","score":0.557164192199707},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5212122201919556},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.49231278896331787},{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.44969093799591064},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4199257791042328},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.2649819850921631},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19197392463684082},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.11740797758102417}],"concepts":[{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.9473560452461243},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.6089440584182739},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.5795714259147644},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5706673860549927},{"id":"https://openalex.org/C2778439541","wikidata":"https://www.wikidata.org/wiki/Q7106412","display_name":"Oscillation (cell signaling)","level":2,"score":0.557164192199707},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5212122201919556},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.49231278896331787},{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.44969093799591064},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4199257791042328},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.2649819850921631},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19197392463684082},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.11740797758102417},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas.2004.1328313","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2004.1328313","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","raw_type":"proceedings-article"},{"id":"pmh:oai:acervodigital.unesp.br:11449/67875","is_oa":false,"landing_page_url":"http://acervodigital.unesp.br/handle/11449/67875","pdf_url":null,"source":{"id":"https://openalex.org/S4306400256","display_name":"Acervo Digital da Universidade Estadual Paulista (Universidade Estadual Paulista)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210115194","host_organization_name":"Funda\u00e7\u00e3o para o Desenvolvimento da UNESP","host_organization_lineage":["https://openalex.org/I4210115194"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"outro"},{"id":"pmh:oai:repositorio.unesp.br:11449/67875","is_oa":true,"landing_page_url":"http://hdl.handle.net/11449/67875","pdf_url":null,"source":{"id":"https://openalex.org/S4377196277","display_name":"UNESP Institutional Repository (S\u00e3o Paulo State University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I879563668","host_organization_name":"Universidade Estadual Paulista (Unesp)","host_organization_lineage":["https://openalex.org/I879563668"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferencePaper"}],"best_oa_location":{"id":"pmh:oai:repositorio.unesp.br:11449/67875","is_oa":true,"landing_page_url":"http://hdl.handle.net/11449/67875","pdf_url":null,"source":{"id":"https://openalex.org/S4377196277","display_name":"UNESP Institutional Repository (S\u00e3o Paulo State University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I879563668","host_organization_name":"Universidade Estadual Paulista (Unesp)","host_organization_lineage":["https://openalex.org/I879563668"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferencePaper"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7900000214576721,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1627613727","https://openalex.org/W2062327827","https://openalex.org/W2135585706","https://openalex.org/W2143477947","https://openalex.org/W6681340094"],"related_works":["https://openalex.org/W2380467267","https://openalex.org/W1980525453","https://openalex.org/W2976219355","https://openalex.org/W2325206724","https://openalex.org/W3129408886","https://openalex.org/W4233090067","https://openalex.org/W2365946217","https://openalex.org/W2103754166","https://openalex.org/W2043945969","https://openalex.org/W1964543336"],"abstract_inverted_index":{"A":[0,53],"quasi-sinusoidal":[1],"linearly":[2],"tunable":[3],"OTA-C":[4],"VCO":[5,48,67,112],"built":[6],"with":[7,21,88,131],"triode-region":[8],"transconductors":[9],"is":[10,15,40,85,96,102,116],"presented.":[11],"Oscillation":[12],"upon":[13],"power-on":[14],"ensured":[16],"by":[17,118],"RHP":[18],"poles":[19],"associated":[20],"gate-drain":[22],"capacitances":[23],"of":[24,43,55,63,79,110,135],"OTA":[25,30],"input":[26],"devices.":[27],"Since":[28],"the":[29,33,35,47,58,66,111],"nonlinearity":[31],"stabilizes":[32],"amplitude,":[34],"oscillation":[36],"frequency":[37],"f/sub":[38,83],"0/":[39,84],"first-order":[41],"independent":[42],"V/sub":[44,94,129],"DD/,":[45],"making":[46],"adequate":[49],"to":[50,93],"mixed-mode":[51],"designs.":[52],"range":[54],"simulations":[56],"attests":[57],"theoretical":[59],"analysis.":[60],"As":[61],"part":[62],"a":[64,71,119,123,132],"DPLL,":[65],"was":[68],"prototyped":[69],"on":[70,122],"0.8/spl":[72],"mu/m":[73,125],"CMOS":[74,126],"process,":[75],"occupying":[76],"an":[77],"area":[78],"0.15mm/sup":[80],"2/.":[81],"Nominal":[82],"1":[86],"MHz,":[87],"K/sub":[89],"VCO/=8.4KHz/mV.":[90],"Measured":[91],"sensitivity":[92],"DD/":[95],"below":[97],"2.17,":[98],"while":[99],"phase":[100],"noise":[101],"-86dBc":[103],"at":[104],"100":[105],"kHz":[106],"offset.":[107],"The":[108],"feasibility":[109],"for":[113],"higher":[114],"frequencies":[115],"verified":[117],"redesign":[120],"based":[121],"0.35/spl":[124],"process":[127],"and":[128],"DD/=3.3V,":[130],"linear":[133],"frequency-span":[134],"13.2":[136],"MHz-61.5":[137],"MHz.":[138]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
