{"id":"https://openalex.org/W2140490954","doi":"https://doi.org/10.1109/iscas.2003.1206443","title":"Design of a reduced KII set and network in analog VLSI","display_name":"Design of a reduced KII set and network in analog VLSI","publication_year":2003,"publication_date":"2003-11-04","ids":{"openalex":"https://openalex.org/W2140490954","doi":"https://doi.org/10.1109/iscas.2003.1206443","mag":"2140490954"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2003.1206443","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206443","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089059760","display_name":"Dongming Xu","orcid":"https://orcid.org/0000-0001-7515-4977"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Dongming Xu","raw_affiliation_strings":["Computational NeuroEngineering Laboratory, University of Florida, Gainesville, FL, USA","Computational NeuroEngineering Lab., Florida Univ., Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"Computational NeuroEngineering Laboratory, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Computational NeuroEngineering Lab., Florida Univ., Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006353150","display_name":"Liping Deng","orcid":"https://orcid.org/0000-0001-6903-3239"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Liping Deng","raw_affiliation_strings":["Computational NeuroEngineering Laboratory, University of Florida, Gainesville, FL, USA","Computational NeuroEngineering Lab., Florida Univ., Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"Computational NeuroEngineering Laboratory, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Computational NeuroEngineering Lab., Florida Univ., Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113319313","display_name":"J.G. Harris","orcid":null},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.G. Harris","raw_affiliation_strings":["Computational NeuroEngineering Laboratory, University of Florida, Gainesville, FL, USA","Computational NeuroEngineering Lab., Florida Univ., Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"Computational NeuroEngineering Laboratory, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Computational NeuroEngineering Lab., Florida Univ., Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019504861","display_name":"Jos\u00e9 C. Pr\u0131\u0301ncipe","orcid":"https://orcid.org/0000-0002-3449-3531"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.C. Principe","raw_affiliation_strings":["Computational NeuroEngineering Laboratory, University of Florida, Gainesville, FL, USA","Computational NeuroEngineering Lab., Florida Univ., Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"Computational NeuroEngineering Laboratory, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Computational NeuroEngineering Lab., Florida Univ., Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5089059760"],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":0.1074,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.3727657,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"5","issue":null,"first_page":"V","last_page":"837"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},"topics":[{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10581","display_name":"Neural dynamics and brain function","score":0.991100013256073,"subfield":{"id":"https://openalex.org/subfields/2805","display_name":"Cognitive Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7324378490447998},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7134503126144409},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6237176060676575},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.5900757908821106},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5890892744064331},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4681413769721985},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44049888849258423},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.41838499903678894},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41528135538101196},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.35026097297668457},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3408810496330261},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32373934984207153},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15482360124588013},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09608766436576843},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07774853706359863}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7324378490447998},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7134503126144409},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6237176060676575},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.5900757908821106},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5890892744064331},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4681413769721985},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44049888849258423},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.41838499903678894},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41528135538101196},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.35026097297668457},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3408810496330261},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32373934984207153},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15482360124588013},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09608766436576843},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07774853706359863},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2003.1206443","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206443","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.493.1960","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.493.1960","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cnel.ufl.edu/hybrid/_private/publications/kiinetavlsi_01206443.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2025116405","https://openalex.org/W2062258383","https://openalex.org/W2135231483","https://openalex.org/W2157586514","https://openalex.org/W3142790270","https://openalex.org/W6682961064","https://openalex.org/W6792599741","https://openalex.org/W7065245920"],"related_works":["https://openalex.org/W2098218272","https://openalex.org/W2134640991","https://openalex.org/W3027318491","https://openalex.org/W1979789826","https://openalex.org/W1986774039","https://openalex.org/W4244547561","https://openalex.org/W2502691491","https://openalex.org/W2115579119","https://openalex.org/W2017236304","https://openalex.org/W3142211975"],"abstract_inverted_index":{"This":[0],"paper":[1,41],"focuses":[2],"on":[3],"the":[4,21,25,47,65,74,77,80,88,91,97,103,123],"analog":[5],"VLSI":[6],"design":[7,49,108],"of":[8,24,50,79,90,99],"a":[9,54,61,106],"reduced":[10,55,124],"KII":[11,56,66,104,125],"set":[12,57],"and":[13,76,94,117],"network,":[14,105],"which":[15],"are":[16,71,120],"basic":[17],"building":[18],"blocks":[19,52,112],"in":[20,37,46,53,102],"computational":[22],"model":[23],"olfactory":[26],"cortex":[27],"proposed":[28],"by":[29],"Walter":[30],"Freeman.":[31],"Previous":[32],"implementation":[33],"issues":[34],"were":[35],"discussed":[36],"2001,":[38],"but":[39],"this":[40],"will":[42],"present":[43],"recent":[44],"developments":[45],"circuit":[48],"individual":[51],"as":[58,60],"well":[59],"system":[62],"architecture":[63],"for":[64,122],"network.":[67],"The":[68],"coupling":[69],"coefficients":[70],"built":[72],"into":[73],"chip":[75,118],"shape":[78],"nonlinear":[81,92,111],"block":[82,93],"is":[83,113],"controlled":[84],"externally.":[85],"To":[86],"improve":[87],"efficiency":[89],"to":[95,109],"reduce":[96],"problem":[98],"massive":[100],"interconnections":[101],"mixed-signal":[107],"multiplex":[110],"proposed.":[114],"Simulation":[115],"results":[116],"measurement":[119],"presented":[121],"set.":[126]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
