{"id":"https://openalex.org/W2149622198","doi":"https://doi.org/10.1109/iscas.2003.1206230","title":"An efficient transistor optimizer for custom circuits","display_name":"An efficient transistor optimizer for custom circuits","publication_year":2003,"publication_date":"2003-11-04","ids":{"openalex":"https://openalex.org/W2149622198","doi":"https://doi.org/10.1109/iscas.2003.1206230","mag":"2149622198"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2003.1206230","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206230","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100695163","display_name":"Xiaoyan Yu","orcid":"https://orcid.org/0000-0003-0351-8393"},"institutions":[{"id":"https://openalex.org/I4210094759","display_name":"Fujitsu (United States)","ror":"https://ror.org/0073whr05","country_code":"US","type":"company","lineage":["https://openalex.org/I2252096349","https://openalex.org/I4210094759"]},{"id":"https://openalex.org/I84218800","display_name":"University of California, Davis","ror":"https://ror.org/05rrcem69","country_code":"US","type":"education","lineage":["https://openalex.org/I84218800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiao Yan Yu","raw_affiliation_strings":["ACSEL Laboratory, University of California, Davis, CA, USA","Advanced LSI Research, Fujitsu Laboratory of America, Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ACSEL Laboratory, University of California, Davis, CA, USA","institution_ids":["https://openalex.org/I84218800"]},{"raw_affiliation_string":"Advanced LSI Research, Fujitsu Laboratory of America, Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210094759"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010898738","display_name":"Vojin G. Oklobdzija","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094759","display_name":"Fujitsu (United States)","ror":"https://ror.org/0073whr05","country_code":"US","type":"company","lineage":["https://openalex.org/I2252096349","https://openalex.org/I4210094759"]},{"id":"https://openalex.org/I84218800","display_name":"University of California, Davis","ror":"https://ror.org/05rrcem69","country_code":"US","type":"education","lineage":["https://openalex.org/I84218800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V.G. Oklobdzija","raw_affiliation_strings":["ACSEL Laboratory, University of California, Davis, CA, USA","Advanced LSI Research, Fujitsu Laboratory of America, Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ACSEL Laboratory, University of California, Davis, CA, USA","institution_ids":["https://openalex.org/I84218800"]},{"raw_affiliation_string":"Advanced LSI Research, Fujitsu Laboratory of America, Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210094759"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006168492","display_name":"William W. Walker","orcid":"https://orcid.org/0009-0006-6905-3217"},"institutions":[{"id":"https://openalex.org/I4210094759","display_name":"Fujitsu (United States)","ror":"https://ror.org/0073whr05","country_code":"US","type":"company","lineage":["https://openalex.org/I2252096349","https://openalex.org/I4210094759"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W.W. Walker","raw_affiliation_strings":["Advanced LSI Research, Fujitsu Laboratory of America, Sunnyvale, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced LSI Research, Fujitsu Laboratory of America, Sunnyvale, CA","institution_ids":["https://openalex.org/I4210094759"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.4171,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.83115318,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"5","issue":null,"first_page":"V","last_page":"197"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.8098883628845215},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8016257286071777},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7209075689315796},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7041152119636536},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6047053337097168},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.583305835723877},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49901890754699707},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.4922107756137848},{"id":"https://openalex.org/keywords/transistor-model","display_name":"Transistor model","score":0.4809347987174988},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.44837886095046997},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.41494351625442505},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.34917181730270386},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17171087861061096},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15480050444602966},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.13240081071853638},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12617698311805725},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07221043109893799}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.8098883628845215},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8016257286071777},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7209075689315796},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7041152119636536},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6047053337097168},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.583305835723877},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49901890754699707},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.4922107756137848},{"id":"https://openalex.org/C150169584","wikidata":"https://www.wikidata.org/wiki/Q7834319","display_name":"Transistor model","level":4,"score":0.4809347987174988},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.44837886095046997},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.41494351625442505},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.34917181730270386},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17171087861061096},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15480050444602966},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.13240081071853638},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12617698311805725},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07221043109893799},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2003.1206230","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206230","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6499999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W196500522","https://openalex.org/W561944307","https://openalex.org/W1484000312","https://openalex.org/W1817545098","https://openalex.org/W2088115909","https://openalex.org/W2104733895","https://openalex.org/W2119995990","https://openalex.org/W2133247319","https://openalex.org/W2188838890","https://openalex.org/W2325850497","https://openalex.org/W2506592826","https://openalex.org/W2533043278","https://openalex.org/W3004157836","https://openalex.org/W4256152027","https://openalex.org/W4285719527","https://openalex.org/W6638491868","https://openalex.org/W6672852001","https://openalex.org/W6701575323"],"related_works":["https://openalex.org/W2059812140","https://openalex.org/W4235807419","https://openalex.org/W2144633290","https://openalex.org/W3131741930","https://openalex.org/W2610514210","https://openalex.org/W90892980","https://openalex.org/W2550704533","https://openalex.org/W2827496155","https://openalex.org/W2594032196","https://openalex.org/W2890026549"],"abstract_inverted_index":{"We":[0,49],"present":[1],"an":[2],"equation-based":[3],"transistor":[4,29],"size":[5],"optimizer":[6],"that":[7,72],"minimizes":[8],"delay":[9,71],"of":[10],"custom":[11],"circuits.":[12],"Our":[13],"method":[14],"uses":[15],"static":[16],"timing":[17],"analysis":[18],"to":[19,27],"find":[20],"the":[21],"critical":[22,69],"paths":[23],"and":[24,42,53,67],"numerical":[25],"methods":[26],"optimize":[28],"sizes":[30],"continuously":[31],"without":[32],"using":[33],"simulation.":[34],"Consequently,":[35],"it":[36],"is":[37],"faster":[38],"than":[39,45],"simulation-based":[40],"optimizers,":[41],"more":[43],"general":[44],"standard":[46],"cell":[47],"optimizers.":[48],"demonstrate":[50],"its":[51],"efficacy":[52],"accuracy":[54],"on":[55],"a":[56,64],"complete":[57],"dynamic":[58],"adder":[59],"presented,":[60],"where":[61],"we":[62],"achieve":[63],"54%":[65],"speed-up,":[66],"final":[68],"path":[70],"match":[73],"Spice":[74],"within":[75],"1%.":[76]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
