{"id":"https://openalex.org/W2118165687","doi":"https://doi.org/10.1109/iscas.2003.1206228","title":"A coding method for 123 decision diagram pass transistor logic circuit synthesis","display_name":"A coding method for 123 decision diagram pass transistor logic circuit synthesis","publication_year":2003,"publication_date":"2003-11-04","ids":{"openalex":"https://openalex.org/W2118165687","doi":"https://doi.org/10.1109/iscas.2003.1206228","mag":"2118165687"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2003.1206228","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206228","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046511106","display_name":"Mutlu Avc\u0131","orcid":"https://orcid.org/0000-0002-4412-4764"},"institutions":[{"id":"https://openalex.org/I4101805","display_name":"Y\u0131ld\u0131z Technical University","ror":"https://ror.org/0547yzj13","country_code":"TR","type":"education","lineage":["https://openalex.org/I4101805"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"M. Avci","raw_affiliation_strings":["Electronics and Communication Engineering Department, Yildiz Technical University, Besiktas, Istanbul, TURKEY","Electron. & Commun. Eng. Dept., Yildiz Univ., Istanbul, Turkey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Communication Engineering Department, Yildiz Technical University, Besiktas, Istanbul, TURKEY","institution_ids":["https://openalex.org/I4101805"]},{"raw_affiliation_string":"Electron. & Commun. Eng. Dept., Yildiz Univ., Istanbul, Turkey","institution_ids":["https://openalex.org/I4101805"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081154924","display_name":"T\u00fclay Y\u0131ld\u0131r\u0131m","orcid":"https://orcid.org/0000-0001-9993-5583"},"institutions":[{"id":"https://openalex.org/I4101805","display_name":"Y\u0131ld\u0131z Technical University","ror":"https://ror.org/0547yzj13","country_code":"TR","type":"education","lineage":["https://openalex.org/I4101805"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"T. Yildirim","raw_affiliation_strings":["Electronics and Communication Engineering Department, Yildiz Technical University, Besiktas, Istanbul, TURKEY","Electron. & Commun. Eng. Dept., Yildiz Univ., Istanbul, Turkey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Communication Engineering Department, Yildiz Technical University, Besiktas, Istanbul, TURKEY","institution_ids":["https://openalex.org/I4101805"]},{"raw_affiliation_string":"Electron. & Commun. Eng. Dept., Yildiz Univ., Istanbul, Turkey","institution_ids":["https://openalex.org/I4101805"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4101805"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18488349,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"5","issue":null,"first_page":"V","last_page":"189"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9944000244140625,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.7702620029449463},{"id":"https://openalex.org/keywords/binary-decision-diagram","display_name":"Binary decision diagram","score":0.7339422702789307},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.6038439869880676},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5673472285270691},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.561147153377533},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.5195910930633545},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5066602826118469},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49016937613487244},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4824026823043823},{"id":"https://openalex.org/keywords/circuit-diagram","display_name":"Circuit diagram","score":0.4563811421394348},{"id":"https://openalex.org/keywords/diagram","display_name":"Diagram","score":0.44944998621940613},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.449446439743042},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.43110138177871704},{"id":"https://openalex.org/keywords/influence-diagram","display_name":"Influence diagram","score":0.430077463388443},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3879357874393463},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3668176531791687},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3333425521850586},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.29598748683929443},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2624971866607666},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22786006331443787},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22511202096939087},{"id":"https://openalex.org/keywords/decision-tree","display_name":"Decision tree","score":0.1993057131767273},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10788023471832275}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.7702620029449463},{"id":"https://openalex.org/C3309909","wikidata":"https://www.wikidata.org/wiki/Q864155","display_name":"Binary decision diagram","level":2,"score":0.7339422702789307},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.6038439869880676},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5673472285270691},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.561147153377533},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.5195910930633545},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5066602826118469},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49016937613487244},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4824026823043823},{"id":"https://openalex.org/C39799792","wikidata":"https://www.wikidata.org/wiki/Q1045991","display_name":"Circuit diagram","level":2,"score":0.4563811421394348},{"id":"https://openalex.org/C186399060","wikidata":"https://www.wikidata.org/wiki/Q959962","display_name":"Diagram","level":2,"score":0.44944998621940613},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.449446439743042},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.43110138177871704},{"id":"https://openalex.org/C20837028","wikidata":"https://www.wikidata.org/wiki/Q623966","display_name":"Influence diagram","level":3,"score":0.430077463388443},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3879357874393463},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3668176531791687},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3333425521850586},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.29598748683929443},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2624971866607666},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22786006331443787},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22511202096939087},{"id":"https://openalex.org/C84525736","wikidata":"https://www.wikidata.org/wiki/Q831366","display_name":"Decision tree","level":2,"score":0.1993057131767273},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10788023471832275},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2003.1206228","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206228","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7300000190734863,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W627173706","https://openalex.org/W1496641256","https://openalex.org/W2076941448","https://openalex.org/W2171908844","https://openalex.org/W2208031660","https://openalex.org/W6619996258","https://openalex.org/W6629585307"],"related_works":["https://openalex.org/W2089210394","https://openalex.org/W2103286150","https://openalex.org/W2122917767","https://openalex.org/W4300616421","https://openalex.org/W2205783098","https://openalex.org/W1596417907","https://openalex.org/W1507575448","https://openalex.org/W2017528947","https://openalex.org/W2108122578","https://openalex.org/W2768055417"],"abstract_inverted_index":{"Pass":[0],"transistor":[1],"logic":[2,38],"(PTL)":[3],"circuits":[4],"are":[5],"known":[6],"for":[7,56,81,98],"their":[8],"smaller":[9],"silicon":[10],"area":[11],"usage,":[12],"low":[13],"power":[14],"consumption":[15],"and":[16,94,101],"reduced":[17],"delay":[18],"advantages.":[19],"The":[20],"123":[21,74,104],"decision":[22,75,105],"diagram":[23,83],"is":[24,61,69,107],"a":[25,37,57,91],"very":[26,92],"effective":[27,95],"PTL":[28],"synthesis":[29,100],"tool":[30],"based":[31],"on":[32],"binary":[33],"decisions.":[34],"It":[35],"realizes":[36],"function":[39],"using":[40],"NMOS":[41],"pass":[42],"transistors":[43],"with":[44,103],"CMOS":[45],"restoring":[46],"buffers.":[47],"At":[48],"the":[49,54,73,79,82],"same":[50],"time,":[51],"layout":[52],"of":[53],"circuit":[55,99],"two":[58],"metal":[59],"process":[60],"obtained":[62],"by":[63],"this":[64,89],"diagram.":[65,76],"A":[66],"special":[67],"coding":[68,80,96],"required":[70],"to":[71],"apply":[72],"Until":[77],"now,":[78],"has":[84],"not":[85],"been":[86],"explained.":[87],"In":[88],"paper,":[90],"easy":[93],"method":[97],"simplification":[102],"diagrams":[106],"proposed.":[108]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}