{"id":"https://openalex.org/W2165198008","doi":"https://doi.org/10.1109/iscas.2003.1206195","title":"New dynamic logic-level converters for high performance application","display_name":"New dynamic logic-level converters for high performance application","publication_year":2003,"publication_date":"2003-11-04","ids":{"openalex":"https://openalex.org/W2165198008","doi":"https://doi.org/10.1109/iscas.2003.1206195","mag":"2165198008"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2003.1206195","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047060185","display_name":"Nam-Seog Kim","orcid":"https://orcid.org/0000-0002-1039-5945"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Nam-Seog Kim","raw_affiliation_strings":["Memory Division, Samsung Electronics, SRAM Design, South Korea"],"affiliations":[{"raw_affiliation_string":"Memory Division, Samsung Electronics, SRAM Design, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042819645","display_name":"Yong\u2010Jin Yoon","orcid":"https://orcid.org/0000-0002-3885-4947"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yong-Jin Yoon","raw_affiliation_strings":["Memory Division, Samsung Electronics, SRAM Design, South Korea"],"affiliations":[{"raw_affiliation_string":"Memory Division, Samsung Electronics, SRAM Design, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110232432","display_name":"Uk-Rae Cho","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Uk-Rae Cho","raw_affiliation_strings":["Memory Division, Samsung Electronics, SRAM Design, South Korea"],"affiliations":[{"raw_affiliation_string":"Memory Division, Samsung Electronics, SRAM Design, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077048613","display_name":"Hyun-Geun Byun","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hyun-Geun Byun","raw_affiliation_strings":["Memory Division, Samsung Electronics, SRAM Design, South Korea"],"affiliations":[{"raw_affiliation_string":"Memory Division, Samsung Electronics, SRAM Design, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5047060185"],"corresponding_institution_ids":["https://openalex.org/I2250650973"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.22322416,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"5","issue":null,"first_page":"V","last_page":"93"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.8346594572067261},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.715185284614563},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6226627826690674},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5854664444923401},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5672430992126465},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5665162801742554},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5474940538406372},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.51917564868927},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5029765963554382},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4995391368865967},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.48415881395339966},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4264928102493286},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42054545879364014},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.4155523180961609},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3815940022468567},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28924012184143066},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2630477547645569},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1539827585220337}],"concepts":[{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.8346594572067261},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.715185284614563},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6226627826690674},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5854664444923401},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5672430992126465},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5665162801742554},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5474940538406372},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.51917564868927},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5029765963554382},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4995391368865967},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.48415881395339966},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4264928102493286},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42054545879364014},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.4155523180961609},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3815940022468567},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28924012184143066},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2630477547645569},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1539827585220337},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2003.1206195","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8899999856948853,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1586205518","https://openalex.org/W1895430418","https://openalex.org/W1901587736","https://openalex.org/W2121190917","https://openalex.org/W2171717379","https://openalex.org/W6635041956","https://openalex.org/W6639858931"],"related_works":["https://openalex.org/W2082591327","https://openalex.org/W2580743037","https://openalex.org/W3023368799","https://openalex.org/W2114346412","https://openalex.org/W2159448561","https://openalex.org/W2167525841","https://openalex.org/W2137041830","https://openalex.org/W1900707063","https://openalex.org/W4250383491","https://openalex.org/W2102826383"],"abstract_inverted_index":{"Two":[0],"new":[1],"logic-level":[2,17,45],"converting":[3,26],"circuits":[4],"are":[5,76,138],"presented":[6],"for":[7,47,132],"high":[8],"performance":[9],"application.":[10],"One":[11],"of":[12,37,57,70,92,120,142],"them":[13],"is":[14,33,42,66,123,154],"the":[15,27,64,87,90,93,105,121,129,136,152],"dynamic":[16,44],"converter":[18,46],"(DLC).":[19],"It":[20],"has":[21],"fast":[22],"transition":[23,118],"time":[24,119],"in":[25,151],"logic-level,":[28],"and":[29,86,128],"its":[30],"power":[31],"consumption":[32],"smaller":[34],"than":[35,104,125,140],"that":[36,69,141],"conventional":[38],"approaches.":[39],"The":[40,52,74,84,148],"other":[41],"a":[43,58,79,98],"duty":[48,53,130],"ratio":[49,54],"conserving":[50],"(DDLC).":[51],"or":[55,112],"cycle":[56,131],"level":[59,101,109],"converted":[60,134],"signal":[61,133,145],"generated":[62],"by":[63,135,146],"DDLC":[65,88,137],"equal":[67],"to":[68,78,95],"an":[71,143],"input":[72,144],"signal.":[73],"devices":[75],"applied":[77],"72":[80],"Mb":[81],"DDR":[82],"SRAM.":[83],"DLC":[85,122],"allow":[89],"core":[91],"chip":[94,153],"operate":[96],"at":[97],"lower":[99],"voltage":[100,108],"(1.2":[102],"V)":[103],"I/O":[106],"supply":[107],"(1.5":[110],"V":[111],"1.8":[113],"V).":[114],"In":[115],"this":[116],"application,":[117],"less":[124],"120":[126],"psec,":[127],"higher":[139],"1.1%.":[147],"area":[149],"overhead":[150],"0.03%.":[155]},"counts_by_year":[{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}