{"id":"https://openalex.org/W1808432440","doi":"https://doi.org/10.1109/iscas.2003.1206175","title":"An accurate behavioral model of phase detectors for clock recovery circuits","display_name":"An accurate behavioral model of phase detectors for clock recovery circuits","publication_year":2003,"publication_date":"2003-11-04","ids":{"openalex":"https://openalex.org/W1808432440","doi":"https://doi.org/10.1109/iscas.2003.1206175","mag":"1808432440"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2003.1206175","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206175","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017824622","display_name":"Marco Balsi","orcid":"https://orcid.org/0000-0002-3571-2353"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Balsi","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, University of Roma La Sapienza, Rome, Italy","Dipt. di Ingegneria Elettronica, Univ. di Roma, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, University of Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dipt. di Ingegneria Elettronica, Univ. di Roma, Italy","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030782483","display_name":"Francesco Centurelli","orcid":"https://orcid.org/0000-0003-3880-2546"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Centurelli","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, University of Roma La Sapienza, Rome, Italy","Dipt. di Ingegneria Elettronica, Univ. di Roma, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, University of Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dipt. di Ingegneria Elettronica, Univ. di Roma, Italy","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010336494","display_name":"Giuseppe Scotti","orcid":"https://orcid.org/0000-0002-5650-8212"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Scotti","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, University of Roma La Sapienza, Rome, Italy","Dipt. di Ingegneria Elettronica, Univ. di Roma, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, University of Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dipt. di Ingegneria Elettronica, Univ. di Roma, Italy","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081472410","display_name":"Pasquale Tommasino","orcid":"https://orcid.org/0000-0002-3744-2158"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Tommasino","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, University of Roma La Sapienza, Rome, Italy","Dipt. di Ingegneria Elettronica, Univ. di Roma, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, University of Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dipt. di Ingegneria Elettronica, Univ. di Roma, Italy","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068452963","display_name":"Alessandro Trifiletti","orcid":"https://orcid.org/0000-0001-6231-4273"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Trifiletti","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, University of Roma La Sapienza, Rome, Italy","Dipt. di Ingegneria Elettronica, Univ. di Roma, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, University of Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dipt. di Ingegneria Elettronica, Univ. di Roma, Italy","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I861853513"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":null,"first_page":"IV","last_page":"636"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9901000261306763,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8181729316711426},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.7655818462371826},{"id":"https://openalex.org/keywords/phase-detector","display_name":"Phase detector","score":0.6653462052345276},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6011555194854736},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5558802485466003},{"id":"https://openalex.org/keywords/behavioral-modeling","display_name":"Behavioral modeling","score":0.550485372543335},{"id":"https://openalex.org/keywords/phase","display_name":"Phase (matter)","score":0.5089528560638428},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.48969772458076477},{"id":"https://openalex.org/keywords/clock-recovery","display_name":"Clock recovery","score":0.48795002698898315},{"id":"https://openalex.org/keywords/bipolar-junction-transistor","display_name":"Bipolar junction transistor","score":0.480354905128479},{"id":"https://openalex.org/keywords/phase-frequency-detector","display_name":"Phase frequency detector","score":0.4635542929172516},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4520612955093384},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23522350192070007},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.23097211122512817},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.19461700320243835},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19369757175445557},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.15821996331214905},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1271006464958191},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08700445294380188},{"id":"https://openalex.org/keywords/charge-pump","display_name":"Charge pump","score":0.08181411027908325},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07693842053413391},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.07482072710990906}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8181729316711426},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.7655818462371826},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.6653462052345276},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6011555194854736},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5558802485466003},{"id":"https://openalex.org/C78639753","wikidata":"https://www.wikidata.org/wiki/Q3318160","display_name":"Behavioral modeling","level":2,"score":0.550485372543335},{"id":"https://openalex.org/C44280652","wikidata":"https://www.wikidata.org/wiki/Q104837","display_name":"Phase (matter)","level":2,"score":0.5089528560638428},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.48969772458076477},{"id":"https://openalex.org/C2779835379","wikidata":"https://www.wikidata.org/wiki/Q2348121","display_name":"Clock recovery","level":4,"score":0.48795002698898315},{"id":"https://openalex.org/C23061349","wikidata":"https://www.wikidata.org/wiki/Q188946","display_name":"Bipolar junction transistor","level":4,"score":0.480354905128479},{"id":"https://openalex.org/C2776158855","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase frequency detector","level":5,"score":0.4635542929172516},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4520612955093384},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23522350192070007},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.23097211122512817},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.19461700320243835},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19369757175445557},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.15821996331214905},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1271006464958191},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08700445294380188},{"id":"https://openalex.org/C114825011","wikidata":"https://www.wikidata.org/wiki/Q440704","display_name":"Charge pump","level":4,"score":0.08181411027908325},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07693842053413391},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.07482072710990906},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2003.1206175","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206175","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.uniroma1.it:11573/251305","is_oa":false,"landing_page_url":"http://hdl.handle.net/11573/251305","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.699999988079071,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W64772941","https://openalex.org/W575489327","https://openalex.org/W1797924133","https://openalex.org/W1930006379","https://openalex.org/W1993276969","https://openalex.org/W2039419466","https://openalex.org/W2103018069","https://openalex.org/W2107208989","https://openalex.org/W2110623776","https://openalex.org/W2124729073","https://openalex.org/W2124793342","https://openalex.org/W2125980634","https://openalex.org/W2126204627","https://openalex.org/W2144874297","https://openalex.org/W4246804698","https://openalex.org/W6602624816","https://openalex.org/W6616687087","https://openalex.org/W6675754586","https://openalex.org/W6681348732"],"related_works":["https://openalex.org/W3093724499","https://openalex.org/W2144473175","https://openalex.org/W2213169543","https://openalex.org/W2538004191","https://openalex.org/W1964022231","https://openalex.org/W2326841001","https://openalex.org/W2539398064","https://openalex.org/W2104786555","https://openalex.org/W1993932238","https://openalex.org/W1582443377"],"abstract_inverted_index":{"We":[0],"propose":[1],"in":[2,52,75],"this":[3],"paper":[4],"a":[5,58,67,84],"behavioral":[6,47],"modeling":[7],"technique":[8,63],"of":[9,23,36,49,57],"analog":[10],"phase":[11,38,56,69],"detectors":[12],"for":[13,46,71],"clock":[14,26],"recovery":[15,27],"applications,":[16],"that":[17],"allows":[18],"fast":[19],"but":[20],"accurate":[21],"simulations":[22,35,48],"PLL":[24,51],"and":[25],"systems.":[28],"The":[29,62],"model":[30],"is":[31,64],"extracted":[32],"from":[33],"transistor-level":[34],"the":[37,50,53],"detector":[39,70],"circuit,":[40],"thus":[41],"it":[42],"can":[43],"be":[44],"used":[45],"design":[54,60],"verification":[55],"systematic":[59],"methodology.":[61],"applied":[65],"to":[66],"DRML":[68],"2.5":[72],"Gb/s":[73],"applications":[74],"Si":[76],"BJT":[77],"technology":[78],"(27":[79],"GHz":[80],"f/sub":[81],"T/),":[82],"providing":[83],"rms":[85],"error":[86],"below":[87],"5%.":[88]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}