{"id":"https://openalex.org/W1948757792","doi":"https://doi.org/10.1109/iscas.2003.1206096","title":"Architectures for function evaluation on FPGAs","display_name":"Architectures for function evaluation on FPGAs","publication_year":2003,"publication_date":"2003-10-31","ids":{"openalex":"https://openalex.org/W1948757792","doi":"https://doi.org/10.1109/iscas.2003.1206096","mag":"1948757792"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2003.1206096","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065043189","display_name":"N. Sidahoao","orcid":null},"institutions":[{"id":"https://openalex.org/I4322889","display_name":"Mahanakorn University of Technology","ror":"https://ror.org/05qebwp08","country_code":"TH","type":"education","lineage":["https://openalex.org/I4322889"]}],"countries":["TH"],"is_corresponding":true,"raw_author_name":"N. Sidahoao","raw_affiliation_strings":["Dept. of Electron. Eng., Mahanakorn Univ. of Technol., Bangkok, Thailand","[Dept. of Electron. Eng., Mahanakorn Univ. of Technol., Bangkok, Thailand]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electron. Eng., Mahanakorn Univ. of Technol., Bangkok, Thailand","institution_ids":["https://openalex.org/I4322889"]},{"raw_affiliation_string":"[Dept. of Electron. Eng., Mahanakorn Univ. of Technol., Bangkok, Thailand]","institution_ids":["https://openalex.org/I4322889"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"G.A. Constantinides","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College, London, UK","Department of Electrical and Electronic Engineering, Imperial College, London, Uk"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College, London, Uk","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"P.Y. Cheung","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College, London, UK","Department of Electrical and Electronic Engineering, Imperial College, London, Uk"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College, London, Uk","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5065043189"],"corresponding_institution_ids":["https://openalex.org/I4322889"],"apc_list":null,"apc_paid":null,"fwci":2.1272,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.86539216,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2","issue":null,"first_page":"II","last_page":"804"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.901305079460144},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7114287614822388},{"id":"https://openalex.org/keywords/sine","display_name":"Sine","score":0.6295092701911926},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.5562242269515991},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5557672381401062},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.5225072503089905},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5013976097106934},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4323294758796692},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.41580063104629517},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10041892528533936}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.901305079460144},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7114287614822388},{"id":"https://openalex.org/C186661526","wikidata":"https://www.wikidata.org/wiki/Q13647261","display_name":"Sine","level":2,"score":0.6295092701911926},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.5562242269515991},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5557672381401062},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.5225072503089905},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5013976097106934},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4323294758796692},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.41580063104629517},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10041892528533936},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2003.1206096","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},{"id":"pmh:oai:spiral.imperial.ac.uk:10044/1/687","is_oa":false,"landing_page_url":"http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1206096","pdf_url":null,"source":{"id":"https://openalex.org/S4306401396","display_name":"Spiral (Imperial College London)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I47508984","host_organization_name":"Imperial College London","host_organization_lineage":["https://openalex.org/I47508984"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"807","raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1587217691","https://openalex.org/W1649344707","https://openalex.org/W1767781815","https://openalex.org/W1986396242","https://openalex.org/W2009217237","https://openalex.org/W2089607228","https://openalex.org/W2111730172","https://openalex.org/W2122685238","https://openalex.org/W2162278401","https://openalex.org/W4232621341","https://openalex.org/W6635218997","https://openalex.org/W6684165834"],"related_works":["https://openalex.org/W2024574431","https://openalex.org/W2366554144","https://openalex.org/W2995926156","https://openalex.org/W2063534976","https://openalex.org/W2284838239","https://openalex.org/W2139730103","https://openalex.org/W2154203817","https://openalex.org/W2762083038","https://openalex.org/W2559278389","https://openalex.org/W1948757792"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3],"new":[4],"family":[5],"of":[6,12,20,47,81,84],"architectures":[7],"for":[8,24,60],"multi-cycle":[9],"area-efficient":[10],"evaluation":[11],"elementary":[13],"and":[14,17,41,65,77,86],"composite":[15],"functions,":[16,39],"an":[18,56],"exploration":[19],"the":[21,45,52,75,78,82,89],"design":[22],"tradeoffs":[23],"implementation":[25],"on":[26],"Field":[27],"Programmable":[28],"Gate":[29],"Arrays":[30],"(FPGAs).":[31],"The":[32],"method":[33,59],"is":[34],"exemplified":[35],"with":[36],"two":[37],"common":[38],"sine":[40],"power-of-2.":[42],"To":[43],"test":[44],"performance":[46],"each":[48],"design,":[49],"we":[50],"compare":[51],"proposed":[53,90],"architecture":[54],"to":[55],"established":[57],"table-based":[58],"several":[61],"different":[62],"input":[63],"word-lengths":[64],"output":[66],"precision":[67],"requirements.":[68],"FPGA-based":[69],"results":[70],"are":[71],"presented,":[72],"illustrating":[73],"both":[74],"technology-independent":[76],"technology-specific":[79],"attributes":[80],"tradeoff":[83],"area":[85],"speed":[87],"between":[88],"techniques.":[91]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}