{"id":"https://openalex.org/W1547382623","doi":"https://doi.org/10.1109/iscas.2003.1205831","title":"Design guidelines for reconfigurable multiplier blocks","display_name":"Design guidelines for reconfigurable multiplier blocks","publication_year":2003,"publication_date":"2003-11-04","ids":{"openalex":"https://openalex.org/W1547382623","doi":"https://doi.org/10.1109/iscas.2003.1205831","mag":"1547382623"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2003.1205831","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1205831","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058306867","display_name":"S.S. Demirsoy","orcid":null},"institutions":[{"id":"https://openalex.org/I94951947","display_name":"University of Westminster","ror":"https://ror.org/04ycpbx82","country_code":"GB","type":"education","lineage":["https://openalex.org/I94951947"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"S.S. Demirsoy","raw_affiliation_strings":["Applied DSP and VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","Dept. of Electron. Syst., Westminster Univ., London, UK"],"affiliations":[{"raw_affiliation_string":"Applied DSP and VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","institution_ids":["https://openalex.org/I94951947"]},{"raw_affiliation_string":"Dept. of Electron. Syst., Westminster Univ., London, UK","institution_ids":["https://openalex.org/I94951947"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008198554","display_name":"Andrew G. Dempster","orcid":"https://orcid.org/0000-0003-0881-1548"},"institutions":[{"id":"https://openalex.org/I94951947","display_name":"University of Westminster","ror":"https://ror.org/04ycpbx82","country_code":"GB","type":"education","lineage":["https://openalex.org/I94951947"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"A.G. Dempster","raw_affiliation_strings":["Applied DSP and VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","Dept. of Electron. Syst., Westminster Univ., London, UK"],"affiliations":[{"raw_affiliation_string":"Applied DSP and VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","institution_ids":["https://openalex.org/I94951947"]},{"raw_affiliation_string":"Dept. of Electron. Syst., Westminster Univ., London, UK","institution_ids":["https://openalex.org/I94951947"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063620004","display_name":"\u0130zzet Kale","orcid":"https://orcid.org/0000-0001-5562-6885"},"institutions":[{"id":"https://openalex.org/I94951947","display_name":"University of Westminster","ror":"https://ror.org/04ycpbx82","country_code":"GB","type":"education","lineage":["https://openalex.org/I94951947"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"I. Kale","raw_affiliation_strings":["Applied DSP and VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","Dept. of Electron. Syst., Westminster Univ., London, UK"],"affiliations":[{"raw_affiliation_string":"Applied DSP and VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","institution_ids":["https://openalex.org/I94951947"]},{"raw_affiliation_string":"Dept. of Electron. Syst., Westminster Univ., London, UK","institution_ids":["https://openalex.org/I94951947"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5058306867"],"corresponding_institution_ids":["https://openalex.org/I94951947"],"apc_list":null,"apc_paid":null,"fwci":2.0741,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.87262107,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"4","issue":null,"first_page":"IV","last_page":"293"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.8562638759613037},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.8390834331512451},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7064254283905029},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.6678985953330994},{"id":"https://openalex.org/keywords/subtractor","display_name":"Subtractor","score":0.5654259920120239},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5490803718566895},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5365087985992432},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.47146087884902954},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35218024253845215},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3063991665840149},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12638717889785767},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11631578207015991},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.07290282845497131}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.8562638759613037},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.8390834331512451},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7064254283905029},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.6678985953330994},{"id":"https://openalex.org/C187805909","wikidata":"https://www.wikidata.org/wiki/Q1142401","display_name":"Subtractor","level":4,"score":0.5654259920120239},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5490803718566895},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5365087985992432},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.47146087884902954},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35218024253845215},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3063991665840149},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12638717889785767},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11631578207015991},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.07290282845497131},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/iscas.2003.1205831","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1205831","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},{"id":"pmh:oai:westminsterresearch.westminster.ac.uk:9377y","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ISCAS.2003.1205831","pdf_url":null,"source":{"id":"https://openalex.org/S4306400277","display_name":"WestminsterResearch (University of Westminster)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I94951947","host_organization_name":"University of Westminster","host_organization_lineage":["https://openalex.org/I94951947"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"book-chapter"},{"id":"pmh:oai:westminsterresearch.wmin.ac.uk:959","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4306400277","display_name":"WestminsterResearch (University of Westminster)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I94951947","host_organization_name":"University of Westminster","host_organization_lineage":["https://openalex.org/I94951947"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"Book Section"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.108.6654","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.108.6654","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://westminsterresearch.wmin.ac.uk/959/01/Demirsoy,_Dempster_&_Kale_2003_final.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.491.3687","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.491.3687","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://westminsterresearch.wmin.ac.uk/959/1/Demirsoy_Dempster_Kale_2003_final.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1590193206","https://openalex.org/W2103244632","https://openalex.org/W2129513088","https://openalex.org/W2133135437","https://openalex.org/W2169484940"],"related_works":["https://openalex.org/W3170806431","https://openalex.org/W2357289797","https://openalex.org/W2039899645","https://openalex.org/W2371342700","https://openalex.org/W2327110311","https://openalex.org/W2541509322","https://openalex.org/W2544361057","https://openalex.org/W2363059241","https://openalex.org/W1824649256","https://openalex.org/W2959321197"],"abstract_inverted_index":{"The":[0,45,71],"newly":[1],"proposed":[2],"reconfigurable":[3,97],"multiplier":[4,14,37,72,98],"blocks":[5,15],"offer":[6],"significant":[7],"savings":[8],"in":[9,41],"area":[10,69],"over":[11],"the":[12,29,36,82,85,92,96],"traditional":[13],"for":[16,91],"time-multiplexed":[17],"digital":[18],"filters":[19],"or":[20],"any":[21],"other":[22],"system":[23],"where":[24],"only":[25],"a":[26,42,49,77],"subset":[27],"of":[28,57,76,84,95],"coefficients":[30],"that":[31,60],"can":[32,61],"be":[33],"produced":[34],"by":[35],"block":[38,73,99],"is":[39,87],"needed":[40],"given":[43],"time.":[44],"basic":[46],"structure":[47],"comprises":[48],"multiplexer":[50],"connected":[51],"to":[52,67],"at":[53],"least":[54],"one":[55],"input":[56],"an":[58],"adder/subtractor":[59],"generate":[62],"several":[63],"partial":[64],"products,":[65],"leading":[66],"better":[68],"utilization.":[70],"algorithm":[74],"complexity":[75],"design":[78],"increases":[79],"logarithmically":[80],"as":[81],"number":[83],"multiplexers":[86],"increased.":[88],"Design":[89],"guidelines":[90],"maximum":[93],"utilization":[94],"structures":[100],"are":[101],"also":[102],"presented.":[103]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}