{"id":"https://openalex.org/W1598085051","doi":"https://doi.org/10.1109/iscas.2003.1205827","title":"A design flow for linear-phase fixed-point FIR filters: from the NPRM specifications to a VHDL code","display_name":"A design flow for linear-phase fixed-point FIR filters: from the NPRM specifications to a VHDL code","publication_year":2003,"publication_date":"2003-11-04","ids":{"openalex":"https://openalex.org/W1598085051","doi":"https://doi.org/10.1109/iscas.2003.1205827","mag":"1598085051"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2003.1205827","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1205827","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101721828","display_name":"Chia-Yu Yao","orcid":"https://orcid.org/0000-0001-9771-041X"},"institutions":[{"id":"https://openalex.org/I202968851","display_name":"Huafan University","ror":"https://ror.org/02x5hb316","country_code":"TW","type":"education","lineage":["https://openalex.org/I202968851"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-Yu Yao","raw_affiliation_strings":["Department of Electronic Engineering, Huafan University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Huafan University, Taiwan","institution_ids":["https://openalex.org/I202968851"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032087665","display_name":"Chin-Chih Yeh","orcid":null},"institutions":[{"id":"https://openalex.org/I202968851","display_name":"Huafan University","ror":"https://ror.org/02x5hb316","country_code":"TW","type":"education","lineage":["https://openalex.org/I202968851"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chin-Chih Yeh","raw_affiliation_strings":["Department of Electronic Engineering, Huafan University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Huafan University, Taiwan","institution_ids":["https://openalex.org/I202968851"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090996588","display_name":"Tsuan-Fan Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I202968851","display_name":"Huafan University","ror":"https://ror.org/02x5hb316","country_code":"TW","type":"education","lineage":["https://openalex.org/I202968851"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tsuan-Fan Lin","raw_affiliation_strings":["Department of Electronic Engineering, Huafan University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Huafan University, Taiwan","institution_ids":["https://openalex.org/I202968851"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087874178","display_name":"Hsin-Horng Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I202968851","display_name":"Huafan University","ror":"https://ror.org/02x5hb316","country_code":"TW","type":"education","lineage":["https://openalex.org/I202968851"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hsin-Horng Chen","raw_affiliation_strings":["Department of Electronic Engineering, Huafan University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Huafan University, Taiwan","institution_ids":["https://openalex.org/I202968851"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065306431","display_name":"Chiang\u2010Ju Chien","orcid":"https://orcid.org/0000-0001-8672-0014"},"institutions":[{"id":"https://openalex.org/I202968851","display_name":"Huafan University","ror":"https://ror.org/02x5hb316","country_code":"TW","type":"education","lineage":["https://openalex.org/I202968851"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chiang-Ju Chien","raw_affiliation_strings":["Department of Electronic Engineering, Huafan University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Huafan University, Taiwan","institution_ids":["https://openalex.org/I202968851"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I202968851"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.08339829,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"4","issue":null,"first_page":"IV","last_page":"277"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7817012667655945},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7343660593032837},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.7106871008872986},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.631903350353241},{"id":"https://openalex.org/keywords/linear-phase","display_name":"Linear phase","score":0.6086329221725464},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.43867647647857666},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4330999255180359},{"id":"https://openalex.org/keywords/ripple","display_name":"Ripple","score":0.42043113708496094},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.39848577976226807},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28088539838790894},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2607317566871643},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.16955164074897766},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09904012084007263},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07590687274932861},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07572948932647705}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7817012667655945},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7343660593032837},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.7106871008872986},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.631903350353241},{"id":"https://openalex.org/C20610874","wikidata":"https://www.wikidata.org/wiki/Q512136","display_name":"Linear phase","level":3,"score":0.6086329221725464},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.43867647647857666},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4330999255180359},{"id":"https://openalex.org/C2779599953","wikidata":"https://www.wikidata.org/wiki/Q1776117","display_name":"Ripple","level":3,"score":0.42043113708496094},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.39848577976226807},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28088539838790894},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2607317566871643},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.16955164074897766},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09904012084007263},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07590687274932861},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07572948932647705},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2003.1205827","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1205827","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1488554773","https://openalex.org/W1857733903","https://openalex.org/W1965846060","https://openalex.org/W2017483013","https://openalex.org/W2023170313","https://openalex.org/W2096479326","https://openalex.org/W2103244632","https://openalex.org/W2118072362","https://openalex.org/W2119529071","https://openalex.org/W2127539731","https://openalex.org/W2130846531","https://openalex.org/W2154656381","https://openalex.org/W2168772589","https://openalex.org/W2169484940","https://openalex.org/W2169792033","https://openalex.org/W6629207739","https://openalex.org/W6639006346","https://openalex.org/W6656432023","https://openalex.org/W6685117948"],"related_works":["https://openalex.org/W3082309838","https://openalex.org/W3141056701","https://openalex.org/W2163053405","https://openalex.org/W2105612491","https://openalex.org/W1992367381","https://openalex.org/W2034737946","https://openalex.org/W2037573176","https://openalex.org/W3007580271","https://openalex.org/W224313861","https://openalex.org/W2016988675"],"abstract_inverted_index":{"This":[0],"work":[1],"combines":[2],"two":[3],"distinct":[4],"research":[5],"efforts,":[6],"the":[7,11,24,29,37,54,61,70],"coefficient":[8],"design":[9,21],"and":[10],"adder-number":[12],"reduction,":[13],"of":[14,56],"fixed-point":[15],"FIR":[16,62,71],"filters":[17],"into":[18],"an":[19],"automatic":[20],"flow.":[22],"Given":[23],"normalized":[25],"peak-ripple-magnitude":[26],"(NPRM)":[27],"specifications,":[28],"canonic-signed-digit":[30],"(CSD)":[31],"filter":[32,72],"coefficients":[33],"are":[34],"calculated":[35],"by":[36],"partial":[38],"mixed-integer-linear-programming":[39],"(PMILP)":[40],"algorithm.":[41],"Then":[42],"a":[43,65],"signed":[44],"common":[45],"subexpression":[46],"sharing":[47],"(SCSS)":[48],"algorithm":[49],"is":[50,76],"used":[51],"to":[52,59],"reduce":[53],"number":[55],"adders":[57],"required":[58],"implement":[60],"filter.":[63],"Finally":[64],"VHDL":[66],"code":[67],"that":[68],"describes":[69],"hardware":[73],"with":[74],"SCSS":[75],"generated.":[77]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}