{"id":"https://openalex.org/W1686457298","doi":"https://doi.org/10.1109/iscas.2003.1205689","title":"Extremely low supply voltage circuits based on quasi-floating gate supply voltage boosting","display_name":"Extremely low supply voltage circuits based on quasi-floating gate supply voltage boosting","publication_year":2003,"publication_date":"2003-10-31","ids":{"openalex":"https://openalex.org/W1686457298","doi":"https://doi.org/10.1109/iscas.2003.1205689","mag":"1686457298"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2003.1205689","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1205689","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051198669","display_name":"F. Mu\u00f1oz","orcid":"https://orcid.org/0000-0002-9406-3779"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"F. Munoz","raw_affiliation_strings":["Departamento de Ingenieria Electronica, Universidad de Sevilla, Spain","Departamento de Ingenieria Electronica, Univ. de Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Ingenieria Electronica, Universidad de Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]},{"raw_affiliation_string":"Departamento de Ingenieria Electronica, Univ. de Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084248588","display_name":"Antonio J. L\u00f3pez\u2010Mart\u00edn","orcid":"https://orcid.org/0000-0001-7629-0305"},"institutions":[{"id":"https://openalex.org/I88155538","display_name":"Universidad de Navarra","ror":"https://ror.org/02rxc7m23","country_code":"ES","type":"education","lineage":["https://openalex.org/I88155538"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"A. Lopez-Martin","raw_affiliation_strings":["Departamento de Ingenieria Electrica, Universidad Politecnica de Navarra, Pamplona, Spain","[Departamento de Ingenieria Electrica, Universidad Politecnica de Navarra, Pamplona, Spain]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Ingenieria Electrica, Universidad Politecnica de Navarra, Pamplona, Spain","institution_ids":["https://openalex.org/I88155538"]},{"raw_affiliation_string":"[Departamento de Ingenieria Electrica, Universidad Politecnica de Navarra, Pamplona, Spain]","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089442866","display_name":"R.G. Carvajal","orcid":"https://orcid.org/0000-0003-3891-8987"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"R.G. Carvajal","raw_affiliation_strings":["Departamento de Ingenieria Electronica, Universidad de Sevilla, Spain","Departamento de Ingenier\u00eda Electr\u00f3nica Universidad de Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Ingenieria Electronica, Universidad de Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]},{"raw_affiliation_string":"Departamento de Ingenier\u00eda Electr\u00f3nica Universidad de Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066106035","display_name":"J. Ramirez-Angulol","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Ramirez-Angulol","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078762976","display_name":"A. Torralba","orcid":"https://orcid.org/0000-0001-6887-6146"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"A. Torralba","raw_affiliation_strings":["Departamento de Ingenieria Electronica, Universidad de Sevilla, Spain","Departamento de Ingenier\u00eda Electr\u00f3nica Universidad de Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Ingenieria Electronica, Universidad de Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]},{"raw_affiliation_string":"Departamento de Ingenier\u00eda Electr\u00f3nica Universidad de Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009624800","display_name":"M. Kachare","orcid":null},"institutions":[{"id":"https://openalex.org/I10052268","display_name":"New Mexico State University","ror":"https://ror.org/00hpz7z43","country_code":"US","type":"education","lineage":["https://openalex.org/I10052268"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Kachare","raw_affiliation_strings":["Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA","Klipsch School of Electrical and Computer Engineering, New Mexico State University Las Cruces, NM, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA","institution_ids":["https://openalex.org/I10052268"]},{"raw_affiliation_string":"Klipsch School of Electrical and Computer Engineering, New Mexico State University Las Cruces, NM, USA","institution_ids":["https://openalex.org/I10052268"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021698710","display_name":"B. Palomo","orcid":"https://orcid.org/0000-0003-3549-3266"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"B. Palomo","raw_affiliation_strings":["Departamento de Ingenieria Electronica, Universidad de Sevilla, Spain","Departamento de Ingenier\u00eda Electr\u00f3nica Universidad de Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Ingenieria Electronica, Universidad de Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]},{"raw_affiliation_string":"Departamento de Ingenier\u00eda Electr\u00f3nica Universidad de Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6003,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.62212846,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"I","last_page":"817"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.625954270362854},{"id":"https://openalex.org/keywords/overdrive-voltage","display_name":"Overdrive voltage","score":0.6115131378173828},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6023656725883484},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.580359697341919},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5779255628585815},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5581759810447693},{"id":"https://openalex.org/keywords/dropout-voltage","display_name":"Dropout voltage","score":0.5470531582832336},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.5240000486373901},{"id":"https://openalex.org/keywords/low-voltage","display_name":"Low voltage","score":0.4817093014717102},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.43694251775741577},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43604904413223267},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.396686315536499},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.38819146156311035},{"id":"https://openalex.org/keywords/voltage-divider","display_name":"Voltage divider","score":0.36885297298431396},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3253285884857178}],"concepts":[{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.625954270362854},{"id":"https://openalex.org/C195905723","wikidata":"https://www.wikidata.org/wiki/Q7113634","display_name":"Overdrive voltage","level":5,"score":0.6115131378173828},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6023656725883484},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.580359697341919},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5779255628585815},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5581759810447693},{"id":"https://openalex.org/C15032970","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Dropout voltage","level":4,"score":0.5470531582832336},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.5240000486373901},{"id":"https://openalex.org/C128624480","wikidata":"https://www.wikidata.org/wiki/Q1504817","display_name":"Low voltage","level":3,"score":0.4817093014717102},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43694251775741577},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43604904413223267},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.396686315536499},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.38819146156311035},{"id":"https://openalex.org/C49324399","wikidata":"https://www.wikidata.org/wiki/Q466758","display_name":"Voltage divider","level":3,"score":0.36885297298431396},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3253285884857178}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2003.1205689","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1205689","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8199999928474426}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W593715794","https://openalex.org/W1961300835","https://openalex.org/W2033021170","https://openalex.org/W2105544656","https://openalex.org/W2145135294","https://openalex.org/W6617657390","https://openalex.org/W6658641950"],"related_works":["https://openalex.org/W4292868060","https://openalex.org/W2024816799","https://openalex.org/W2044172536","https://openalex.org/W2127578324","https://openalex.org/W2091326629","https://openalex.org/W3209480941","https://openalex.org/W3196410233","https://openalex.org/W3106621756","https://openalex.org/W2367229640","https://openalex.org/W2519085851"],"abstract_inverted_index":{"A":[0],"simple":[1],"scheme":[2],"to":[3,37,64],"boost":[4],"the":[5,11,86],"supply":[6,12,34,61],"voltage":[7,35,62],"above":[8],"and":[9,27],"below":[10],"rails":[13],"is":[14],"introduced.":[15],"Three":[16],"applications":[17],"of":[18,56,67],"this":[19],"technique":[20],"are":[21,82],"discussed:":[22],"a)":[23],"a":[24,32,38,43,52,59,68],"rail-to-rail":[25,45],"sample":[26],"hold":[28],"circuit":[29],"operating":[30,57],"from":[31,74],"single":[33,60],"close":[36,63],"transistor's":[39,69],"threshold":[40,70],"voltage;":[41],"b)":[42],"low-voltage":[44],"switch":[46],"for":[47],"high":[48],"precision":[49],"applications;":[50],"c)":[51],"NAND":[53],"gate":[54],"capable":[55],"with":[58],"one":[65],"half":[66],"voltage.":[71],"Experimental":[72],"results":[73],"prototypes":[75],"in":[76],"1.5":[77],"/spl":[78],"mu/m":[79],"CMOS":[80],"technology":[81],"shown":[83],"that":[84],"verify":[85],"proposed":[87],"approach.":[88]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-31T08:31:51.225901","created_date":"2025-10-10T00:00:00"}
