{"id":"https://openalex.org/W1788602313","doi":"https://doi.org/10.1109/iscas.2003.1205167","title":"Behavioral modeling and simulation of high-speed analog-to-digital converters using SystemC","display_name":"Behavioral modeling and simulation of high-speed analog-to-digital converters using SystemC","publication_year":2003,"publication_date":"2003-11-21","ids":{"openalex":"https://openalex.org/W1788602313","doi":"https://doi.org/10.1109/iscas.2003.1205167","mag":"1788602313"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2003.1205167","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1205167","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010009306","display_name":"J. Bjornsen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210162339","display_name":"Nordic Semiconductor (Norway)","ror":"https://ror.org/05akpxs80","country_code":"NO","type":"company","lineage":["https://openalex.org/I4210162339"]},{"id":"https://openalex.org/I204778367","display_name":"Norwegian University of Science and Technology","ror":"https://ror.org/05xg72x27","country_code":"NO","type":"education","lineage":["https://openalex.org/I204778367"]}],"countries":["NO"],"is_corresponding":true,"raw_author_name":"J. Bjornsen","raw_affiliation_strings":["Department of Physical Electronics, Norwegian Institute of Science and Technology, Trondheim, Norway","Nordic VLSI ASA, Trondheim, Norway"],"affiliations":[{"raw_affiliation_string":"Department of Physical Electronics, Norwegian Institute of Science and Technology, Trondheim, Norway","institution_ids":["https://openalex.org/I204778367"]},{"raw_affiliation_string":"Nordic VLSI ASA, Trondheim, Norway","institution_ids":["https://openalex.org/I4210162339"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055804223","display_name":"Trond Ytterdal","orcid":"https://orcid.org/0000-0002-2109-833X"},"institutions":[{"id":"https://openalex.org/I4210162339","display_name":"Nordic Semiconductor (Norway)","ror":"https://ror.org/05akpxs80","country_code":"NO","type":"company","lineage":["https://openalex.org/I4210162339"]},{"id":"https://openalex.org/I204778367","display_name":"Norwegian University of Science and Technology","ror":"https://ror.org/05xg72x27","country_code":"NO","type":"education","lineage":["https://openalex.org/I204778367"]}],"countries":["NO"],"is_corresponding":false,"raw_author_name":"T. Ytterdal","raw_affiliation_strings":["Department of Physical Electronics, Norwegian Institute of Science and Technology, Trondheim, Norway","Nordic VLSI ASA, Trondheim, Norway"],"affiliations":[{"raw_affiliation_string":"Department of Physical Electronics, Norwegian Institute of Science and Technology, Trondheim, Norway","institution_ids":["https://openalex.org/I204778367"]},{"raw_affiliation_string":"Nordic VLSI ASA, Trondheim, Norway","institution_ids":["https://openalex.org/I4210162339"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5010009306"],"corresponding_institution_ids":["https://openalex.org/I204778367","https://openalex.org/I4210162339"],"apc_list":null,"apc_paid":null,"fwci":0.5875,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.66544464,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"3","issue":null,"first_page":"III","last_page":"906"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9769418239593506},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7893252372741699},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.7304656505584717},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6782811880111694},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6099591851234436},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.5450289249420166},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.5174599289894104},{"id":"https://openalex.org/keywords/behavioral-modeling","display_name":"Behavioral modeling","score":0.4880289137363434},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.44377556443214417},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4211440086364746},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41262006759643555},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.41223642230033875},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.36345094442367554},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.20320257544517517},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09206646680831909},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08814746141433716},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08561065793037415},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08323618769645691}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9769418239593506},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7893252372741699},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.7304656505584717},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6782811880111694},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6099591851234436},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.5450289249420166},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.5174599289894104},{"id":"https://openalex.org/C78639753","wikidata":"https://www.wikidata.org/wiki/Q3318160","display_name":"Behavioral modeling","level":2,"score":0.4880289137363434},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.44377556443214417},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4211440086364746},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41262006759643555},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.41223642230033875},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36345094442367554},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.20320257544517517},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09206646680831909},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08814746141433716},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08561065793037415},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08323618769645691},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2003.1205167","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1205167","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W3966515","https://openalex.org/W13468827","https://openalex.org/W1505760695","https://openalex.org/W1515109292","https://openalex.org/W1579501018","https://openalex.org/W1857383444","https://openalex.org/W2112017015","https://openalex.org/W2115459188","https://openalex.org/W2129189285","https://openalex.org/W2138085499","https://openalex.org/W2184277408","https://openalex.org/W4234589815","https://openalex.org/W6630325297","https://openalex.org/W6677059460"],"related_works":["https://openalex.org/W1525398417","https://openalex.org/W2532163536","https://openalex.org/W2266880325","https://openalex.org/W2069603759","https://openalex.org/W2533881872","https://openalex.org/W3146089259","https://openalex.org/W2167813198","https://openalex.org/W4252858011","https://openalex.org/W2133071611","https://openalex.org/W4238487776"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"a":[3,68],"software":[4],"framework":[5,17,65],"for":[6,34,52],"rapid":[7],"behavioral":[8],"modeling":[9],"and":[10,26,54,75,77],"simulation":[11],"of":[12,43,62,83],"analog-to-digital":[13],"converters":[14],"(ADCs).":[15],"The":[16],"is":[18,73],"based":[19],"on":[20,80],"the":[21,40,44,60,81,84],"SystemC":[22,64],"C++":[23],"class":[24],"libraries":[25],"has":[27],"proven":[28],"to":[29],"be":[30],"an":[31],"effective":[32],"tool":[33],"exploring":[35],"different":[36],"system-level":[37],"architectures":[38],"in":[39],"early":[41],"stages":[42],"design":[45],"process.":[46],"Post-processing":[47],"analysis":[48],"tools":[49],"are":[50],"included":[51],"static":[53],"dynamic":[55],"performance":[56,61],"calculation.":[57],"To":[58],"compare":[59],"our":[63],"with":[66],"Verilog,":[67],"12":[69],"bit":[70],"pipelined":[71],"ADC":[72],"modeled":[74],"simulated,":[76],"we":[78],"report":[79],"results":[82],"comparison.":[85]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
