{"id":"https://openalex.org/W2105101187","doi":"https://doi.org/10.1109/iscas.2002.1010818","title":"Designing multiplier blocks with low logic depth","display_name":"Designing multiplier blocks with low logic depth","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2105101187","doi":"https://doi.org/10.1109/iscas.2002.1010818","mag":"2105101187"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1010818","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010818","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008198554","display_name":"Andrew G. Dempster","orcid":"https://orcid.org/0000-0003-0881-1548"},"institutions":[{"id":"https://openalex.org/I94951947","display_name":"University of Westminster","ror":"https://ror.org/04ycpbx82","country_code":"GB","type":"education","lineage":["https://openalex.org/I94951947"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"A.G. Dempster","raw_affiliation_strings":["University of Westminster, London, UK","University of Westminster, London, UK;"],"affiliations":[{"raw_affiliation_string":"University of Westminster, London, UK","institution_ids":["https://openalex.org/I94951947"]},{"raw_affiliation_string":"University of Westminster, London, UK;","institution_ids":["https://openalex.org/I94951947"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027744015","display_name":"S.S. Dimirsoy","orcid":null},"institutions":[{"id":"https://openalex.org/I94951947","display_name":"University of Westminster","ror":"https://ror.org/04ycpbx82","country_code":"GB","type":"education","lineage":["https://openalex.org/I94951947"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"S.S. Dimirsoy","raw_affiliation_strings":["University of Westminster, London, UK","University of Westminster, London, UK;"],"affiliations":[{"raw_affiliation_string":"University of Westminster, London, UK","institution_ids":["https://openalex.org/I94951947"]},{"raw_affiliation_string":"University of Westminster, London, UK;","institution_ids":["https://openalex.org/I94951947"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063620004","display_name":"\u0130zzet Kale","orcid":"https://orcid.org/0000-0001-5562-6885"},"institutions":[{"id":"https://openalex.org/I94951947","display_name":"University of Westminster","ror":"https://ror.org/04ycpbx82","country_code":"GB","type":"education","lineage":["https://openalex.org/I94951947"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"I. Kale","raw_affiliation_strings":["University of Westminster, London, UK","University of Westminster, London, UK;"],"affiliations":[{"raw_affiliation_string":"University of Westminster, London, UK","institution_ids":["https://openalex.org/I94951947"]},{"raw_affiliation_string":"University of Westminster, London, UK;","institution_ids":["https://openalex.org/I94951947"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5008198554"],"corresponding_institution_ids":["https://openalex.org/I94951947"],"apc_list":null,"apc_paid":null,"fwci":6.2594,"has_fulltext":false,"cited_by_count":99,"citation_normalized_percentile":{"value":0.96740883,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"5","issue":null,"first_page":"V","last_page":"773"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.7169452905654907},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6561142802238464},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.65118807554245},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6324741244316101},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6135877370834351},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5934525728225708},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5484495759010315},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5375701189041138},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.534217894077301},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.5227675437927246},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.49665123224258423},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4787989556789398},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4245007634162903},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3834419846534729},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3395247459411621},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.21693062782287598},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21603691577911377},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18075606226921082},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.15755414962768555},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07309824228286743}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.7169452905654907},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6561142802238464},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.65118807554245},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6324741244316101},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6135877370834351},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5934525728225708},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5484495759010315},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5375701189041138},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.534217894077301},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.5227675437927246},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.49665123224258423},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4787989556789398},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4245007634162903},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3834419846534729},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3395247459411621},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.21693062782287598},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21603691577911377},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18075606226921082},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.15755414962768555},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07309824228286743},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas.2002.1010818","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010818","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},{"id":"pmh:oai:westminsterresearch.wmin.ac.uk:960","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4306400277","display_name":"WestminsterResearch (University of Westminster)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I94951947","host_organization_name":"University of Westminster","host_organization_lineage":["https://openalex.org/I94951947"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"Book Section"},{"id":"pmh:oai:westminsterresearch.westminster.ac.uk:93wq7","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ISCAS.2002.1010818","pdf_url":null,"source":{"id":"https://openalex.org/S4306400277","display_name":"WestminsterResearch (University of Westminster)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I94951947","host_organization_name":"University of Westminster","host_organization_lineage":["https://openalex.org/I94951947"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1507414486","https://openalex.org/W1865434818","https://openalex.org/W1986644367","https://openalex.org/W2037767687","https://openalex.org/W2077881312","https://openalex.org/W2103244632","https://openalex.org/W2105758312","https://openalex.org/W2132536832","https://openalex.org/W2169484940","https://openalex.org/W2171245945","https://openalex.org/W6639150868"],"related_works":["https://openalex.org/W2082591327","https://openalex.org/W2108396794","https://openalex.org/W2017528947","https://openalex.org/W2171566066","https://openalex.org/W2118487491","https://openalex.org/W2155174752","https://openalex.org/W1593138522","https://openalex.org/W2152533674","https://openalex.org/W2108907112","https://openalex.org/W2125567818"],"abstract_inverted_index":{"The":[0],"depth":[1,28,59],"of":[2],"logic":[3,27,58],"in":[4,31],"an":[5],"integrated":[6],"circuit,":[7,11],"particularly":[8],"a":[9],"CMOS":[10],"is":[12],"highly":[13],"correlated":[14],"both":[15],"with":[16,25,56],"power":[17,33,61],"consumption":[18,34],"and":[19,35,46,60],"degraded":[20],"switching":[21,37],"speed.":[22,38],"Hence,":[23],"designs":[24],"low":[26,57],"can":[29],"aid":[30],"reducing":[32],"increasing":[36],"In":[39],"this":[40],"paper":[41],"we":[42],"demonstrate":[43],"how":[44],"new":[45],"modified":[47],"algorithms":[48],"have":[49],"been":[50],"used":[51],"to":[52],"design":[53],"multiplier":[54],"blocks":[55],"consumption.":[62]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":9},{"year":2016,"cited_by_count":7},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":9},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
