{"id":"https://openalex.org/W1758460393","doi":"https://doi.org/10.1109/iscas.2002.1010778","title":"Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics","display_name":"Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1758460393","doi":"https://doi.org/10.1109/iscas.2002.1010778","mag":"1758460393"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1010778","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://idus.us.es/handle//11441/89974","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067253647","display_name":"Ricardo Carmona\u2010Gal\u00e1n","orcid":"https://orcid.org/0000-0002-4230-3988"},"institutions":[{"id":"https://openalex.org/I134820265","display_name":"Consejo Superior de Investigaciones Cient\u00edficas","ror":"https://ror.org/02gfc7t72","country_code":"ES","type":"government","lineage":["https://openalex.org/I134820265"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"R. Carmona","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC), Seville, Spain","Inst. de Microelectron., IMSE-CNM-CSIC, Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC), Seville, Spain","institution_ids":["https://openalex.org/I4210104545"]},{"raw_affiliation_string":"Inst. de Microelectron., IMSE-CNM-CSIC, Sevilla, Spain","institution_ids":["https://openalex.org/I134820265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084429774","display_name":"F. Jim\u00e9nez-Garrido","orcid":null},"institutions":[{"id":"https://openalex.org/I134820265","display_name":"Consejo Superior de Investigaciones Cient\u00edficas","ror":"https://ror.org/02gfc7t72","country_code":"ES","type":"government","lineage":["https://openalex.org/I134820265"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"F. Jimenez-Garrido","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC), Seville, Spain","Inst. de Microelectron., IMSE-CNM-CSIC, Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC), Seville, Spain","institution_ids":["https://openalex.org/I4210104545"]},{"raw_affiliation_string":"Inst. de Microelectron., IMSE-CNM-CSIC, Sevilla, Spain","institution_ids":["https://openalex.org/I134820265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004478970","display_name":"R. Dom\u00ednguez\u2010Castro","orcid":"https://orcid.org/0000-0002-9924-3410"},"institutions":[{"id":"https://openalex.org/I134820265","display_name":"Consejo Superior de Investigaciones Cient\u00edficas","ror":"https://ror.org/02gfc7t72","country_code":"ES","type":"government","lineage":["https://openalex.org/I134820265"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"R. Dominguez-Castro","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC), Seville, Spain","Inst. de Microelectron., IMSE-CNM-CSIC, Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC), Seville, Spain","institution_ids":["https://openalex.org/I4210104545"]},{"raw_affiliation_string":"Inst. de Microelectron., IMSE-CNM-CSIC, Sevilla, Spain","institution_ids":["https://openalex.org/I134820265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006782053","display_name":"S. Espejo","orcid":"https://orcid.org/0000-0003-2609-2663"},"institutions":[{"id":"https://openalex.org/I134820265","display_name":"Consejo Superior de Investigaciones Cient\u00edficas","ror":"https://ror.org/02gfc7t72","country_code":"ES","type":"government","lineage":["https://openalex.org/I134820265"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"S. Espejo","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC), Seville, Spain","Inst. de Microelectron., IMSE-CNM-CSIC, Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC), Seville, Spain","institution_ids":["https://openalex.org/I4210104545"]},{"raw_affiliation_string":"Inst. de Microelectron., IMSE-CNM-CSIC, Sevilla, Spain","institution_ids":["https://openalex.org/I134820265"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029359976","display_name":"\u00c1. Rodr\u00edguez\u2010V\u00e1zquez","orcid":"https://orcid.org/0000-0002-1006-5241"},"institutions":[{"id":"https://openalex.org/I134820265","display_name":"Consejo Superior de Investigaciones Cient\u00edficas","ror":"https://ror.org/02gfc7t72","country_code":"ES","type":"government","lineage":["https://openalex.org/I134820265"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"A. Rodriguez-Vazquez","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC), Seville, Spain","Inst. de Microelectron., IMSE-CNM-CSIC, Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC), Seville, Spain","institution_ids":["https://openalex.org/I4210104545"]},{"raw_affiliation_string":"Inst. de Microelectron., IMSE-CNM-CSIC, Sevilla, Spain","institution_ids":["https://openalex.org/I134820265"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.1545,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.86699631,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"5","issue":null,"first_page":"V","last_page":"613"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7439197897911072},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7264637351036072},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6340141296386719},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6074762344360352},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.5897853374481201},{"id":"https://openalex.org/keywords/vector-processor","display_name":"Vector processor","score":0.49695566296577454},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4844534397125244},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.45652642846107483},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4505704343318939},{"id":"https://openalex.org/keywords/parallel-processing","display_name":"Parallel processing","score":0.4395645558834076},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4296978712081909},{"id":"https://openalex.org/keywords/analog-computer","display_name":"Analog computer","score":0.4226975440979004},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3559008240699768},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.24674654006958008},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16195246577262878},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1486394703388214}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7439197897911072},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7264637351036072},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6340141296386719},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6074762344360352},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.5897853374481201},{"id":"https://openalex.org/C161824985","wikidata":"https://www.wikidata.org/wiki/Q919509","display_name":"Vector processor","level":2,"score":0.49695566296577454},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4844534397125244},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45652642846107483},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4505704343318939},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.4395645558834076},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4296978712081909},{"id":"https://openalex.org/C90915687","wikidata":"https://www.wikidata.org/wiki/Q63759","display_name":"Analog computer","level":2,"score":0.4226975440979004},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3559008240699768},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.24674654006958008},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16195246577262878},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1486394703388214},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2002.1010778","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},{"id":"pmh:oai:idus.us.es:11441/89974","is_oa":true,"landing_page_url":"https://idus.us.es/handle//11441/89974","pdf_url":null,"source":{"id":"https://openalex.org/S4306401665","display_name":"Deposito de Investigacion Universidad de Sevilla (University of Seville)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79238269","host_organization_name":"Universidad de Sevilla","host_organization_lineage":["https://openalex.org/I79238269"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference output"}],"best_oa_location":{"id":"pmh:oai:idus.us.es:11441/89974","is_oa":true,"landing_page_url":"https://idus.us.es/handle//11441/89974","pdf_url":null,"source":{"id":"https://openalex.org/S4306401665","display_name":"Deposito de Investigacion Universidad de Sevilla (University of Seville)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79238269","host_organization_name":"Universidad de Sevilla","host_organization_lineage":["https://openalex.org/I79238269"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference output"},"sustainable_development_goals":[{"score":0.5400000214576721,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W140853475","https://openalex.org/W2007120634","https://openalex.org/W2097834053","https://openalex.org/W2123999640","https://openalex.org/W2171704516","https://openalex.org/W7034219148"],"related_works":["https://openalex.org/W4244547561","https://openalex.org/W2278641756","https://openalex.org/W2042199684","https://openalex.org/W2472012048","https://openalex.org/W2113894844","https://openalex.org/W2118659236","https://openalex.org/W2067512218","https://openalex.org/W2038729084","https://openalex.org/W3148518141","https://openalex.org/W2123707282"],"abstract_inverted_index":{"A":[0,56],"bio-inspired":[1],"model":[2,27],"for":[3,46],"an":[4],"analog":[5,90],"parallel":[6],"array":[7],"processor":[8],"(APAP),":[9],"based":[10],"on":[11,13],"studies":[12],"the":[14,18,29,37,47,73],"vertebrate":[15],"retina,":[16],"permits":[17],"realization":[19],"of":[20,49,76,86],"complex":[21],"spatio-temporal":[22],"dynamics":[23],"in":[24,31,36,53,64,89,94],"VLSI.":[25],"This":[26],"mimics":[28],"way":[30],"which":[32,41],"images":[33],"are":[34,92],"processed":[35],"natural":[38],"visual":[39],"pathway":[40],"renders":[42],"a":[43,78],"feasible":[44],"alternative":[45],"implementation":[48],"early":[50],"vision":[51],"tasks":[52],"standard":[54],"technologies.":[55],"prototype":[57],"chip":[58],"has":[59],"been":[60],"designed":[61],"and":[62,72],"fabricated":[63],"0.5":[65],"/spl":[66],"mu/m":[67],"CMOS.":[68],"Design":[69],"challenges,":[70],"trade-offs":[71],"building":[74],"blocks":[75],"such":[77],"high-complexity":[79],"system":[80],"(0.5/spl":[81],"times/10/sup":[82],"6/":[83],"transistors,":[84],"most":[85],"them":[87],"operating":[88],"mode)":[91],"presented":[93],"this":[95],"paper.":[96]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-08-14T07:06:38.338062","created_date":"2025-10-10T00:00:00"}