{"id":"https://openalex.org/W1904135398","doi":"https://doi.org/10.1109/iscas.2002.1010658","title":"High-speed memory-saving architecture for the embedded block coding in JPEG2000","display_name":"High-speed memory-saving architecture for the embedded block coding in JPEG2000","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1904135398","doi":"https://doi.org/10.1109/iscas.2002.1010658","mag":"1904135398"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1010658","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010658","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108378684","display_name":"Yun-Tai Hsiao","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yun-Tai Hsiao","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103378455","display_name":"Hung-Der Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Der Lin","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055637899","display_name":"Kun-Bin Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kun-Bin Lee","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111437326","display_name":"Chein-Wei Jen","orcid":"https://orcid.org/0000-0003-0568-5056"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chein-Wei Jen","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan","Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Nat. Chiao Tung Univ, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5108378684"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":7.4736,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.97659108,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"5","issue":null,"first_page":"V","last_page":"133"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10688","display_name":"Image and Signal Denoising Methods","score":0.979200005531311,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7293104529380798},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6113531589508057},{"id":"https://openalex.org/keywords/jpeg-2000","display_name":"JPEG 2000","score":0.5878192186355591},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5826111435890198},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.5531354546546936},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4904050827026367},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.48341047763824463},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4547651410102844},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4505765736103058},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.44174546003341675},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4306654632091522},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39479440450668335},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3264045715332031},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2091379165649414},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11856025457382202},{"id":"https://openalex.org/keywords/image-compression","display_name":"Image compression","score":0.09139847755432129},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07621806859970093}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7293104529380798},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6113531589508057},{"id":"https://openalex.org/C69216139","wikidata":"https://www.wikidata.org/wiki/Q931783","display_name":"JPEG 2000","level":5,"score":0.5878192186355591},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5826111435890198},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.5531354546546936},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4904050827026367},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.48341047763824463},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4547651410102844},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4505765736103058},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.44174546003341675},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4306654632091522},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39479440450668335},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3264045715332031},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2091379165649414},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11856025457382202},{"id":"https://openalex.org/C13481523","wikidata":"https://www.wikidata.org/wiki/Q412438","display_name":"Image compression","level":4,"score":0.09139847755432129},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07621806859970093},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2002.1010658","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010658","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1850939858","https://openalex.org/W2053924748","https://openalex.org/W2066437933","https://openalex.org/W2099508083","https://openalex.org/W2132573196","https://openalex.org/W2146771309","https://openalex.org/W2170023599","https://openalex.org/W6675179602","https://openalex.org/W6681507385"],"related_works":["https://openalex.org/W3011443213","https://openalex.org/W298517545","https://openalex.org/W4312291060","https://openalex.org/W2362169398","https://openalex.org/W2601586183","https://openalex.org/W2139353707","https://openalex.org/W2379644889","https://openalex.org/W2167464667","https://openalex.org/W2038051515","https://openalex.org/W2047282939"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,63,67,95],"high-speed,":[4],"memory-saving":[5,22],"architecture":[6,16],"for":[7,73],"the":[8,20,32,42,45,50,53,57,74,85],"embedded":[9],"block":[10],"coding":[11],"algorithm":[12,23],"in":[13,31,60,77,94],"JPEG2000.":[14],"The":[15,88,104],"is":[17,71,91,116],"based":[18],"on":[19],"proposed":[21],"that":[24,52],"can":[25,106],"achieve":[26],"4":[27],"K":[28],"bits":[29],"reduction":[30],"memory":[33],"requirement":[34],"(20%":[35],"less":[36],"than":[37],"conventional":[38],"approaches)":[39],"without":[40],"degrading":[41],"delay":[43],"of":[44,56,118],"critical":[46],"path.":[47],"By":[48],"exploiting":[49],"characteristic":[51],"input":[54],"symbols":[55],"arithmetic":[58],"coder":[59,81],"JPEG200":[61],"have":[62],"highly":[64],"skewed":[65],"distribution,":[66],"simple":[68],"renormalization":[69],"strategy":[70],"adopted":[72],"code-string":[75],"register":[76],"our":[78],"pipelined":[79],"MQ":[80],"design":[82,90],"to":[83,109],"enhance":[84],"clock":[86],"rate.":[87],"overall":[89],"fully":[92],"implemented":[93],"chip":[96,105],"using":[97],"TSMC":[98],"0.35":[99],"/spl":[100],"mu/m":[101],"CMOS":[102],"technology.":[103],"operate":[107],"up":[108],"142":[110],"MHz":[111],"at":[112],"post-layout":[113],"simulation":[114],"and":[115],"capable":[117],"many":[119],"applications.":[120]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}