{"id":"https://openalex.org/W2162597643","doi":"https://doi.org/10.1109/iscas.2002.1010568","title":"High-performance FIR generation based on a timing-driven architecture and component selection method","display_name":"High-performance FIR generation based on a timing-driven architecture and component selection method","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2162597643","doi":"https://doi.org/10.1109/iscas.2002.1010568","mag":"2162597643"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1010568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015100926","display_name":"Jung-Chun Kao","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"J.C.-Y. Kao","raw_affiliation_strings":["Department of Computer Science, Tsinghua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Tsinghua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111949147","display_name":"Chien-Chun Su","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"C.-F. Su","raw_affiliation_strings":["Department of Computer Science, Tsinghua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Tsinghua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056367344","display_name":"A.C.-H. Wu","orcid":"https://orcid.org/0000-0002-0825-1520"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"A.C.-H. Wu","raw_affiliation_strings":["Department of Computer Science, Tsinghua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Tsinghua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":0.4308,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.64226055,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":null,"first_page":"IV","last_page":"759"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.7697149515151978},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6421368718147278},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6139029264450073},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.5097171664237976},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4837077260017395},{"id":"https://openalex.org/keywords/selection","display_name":"Selection (genetic algorithm)","score":0.4664791226387024},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.44383251667022705},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4347877502441406},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42558589577674866},{"id":"https://openalex.org/keywords/ranging","display_name":"Ranging","score":0.4173320233821869},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3507672846317291},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.31032055616378784},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.28663545846939087},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16692990064620972},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.1187586784362793}],"concepts":[{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.7697149515151978},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6421368718147278},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6139029264450073},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.5097171664237976},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4837077260017395},{"id":"https://openalex.org/C81917197","wikidata":"https://www.wikidata.org/wiki/Q628760","display_name":"Selection (genetic algorithm)","level":2,"score":0.4664791226387024},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.44383251667022705},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4347877502441406},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42558589577674866},{"id":"https://openalex.org/C115051666","wikidata":"https://www.wikidata.org/wiki/Q6522493","display_name":"Ranging","level":2,"score":0.4173320233821869},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3507672846317291},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.31032055616378784},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.28663545846939087},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16692990064620972},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.1187586784362793},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2002.1010568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1967923905","https://openalex.org/W1975010502","https://openalex.org/W2051679558","https://openalex.org/W2074779099","https://openalex.org/W2088673893","https://openalex.org/W2112496084","https://openalex.org/W2170710139"],"related_works":["https://openalex.org/W2783354812","https://openalex.org/W4384112194","https://openalex.org/W2103009189","https://openalex.org/W4312958259","https://openalex.org/W2349383066","https://openalex.org/W1969901537","https://openalex.org/W4328132048","https://openalex.org/W1748531671","https://openalex.org/W1975226036","https://openalex.org/W4251728792"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,61],"present":[4],"a":[5,52,63],"timing-driven":[6],"architecture":[7],"and":[8,35,51,57],"component":[9,33],"selection":[10],"method":[11],"for":[12,66],"high-performance":[13,67],"FIR":[14,19,31,49,68,81],"designs.":[15,69],"We":[16],"develop":[17,62],"an":[18],"generator":[20,50],"that":[21,74],"can":[22,79],"generate":[23,80],"Verilog-based":[24],"RTL":[25],"design":[26,64,77],"specifications":[27],"by":[28],"determining":[29],"the":[30,42,48,91],"structure,":[32],"types":[34],"their":[36],"delay":[37],"budgets":[38],"subject":[39],"to":[40,87],"satisfying":[41],"given":[43],"timing":[44],"constraints.":[45],"By":[46],"integrating":[47],"number":[53],"of":[54],"commercial":[55],"RTL/logic":[56],"physical":[58],"synthesis":[59],"tools,":[60],"environment":[65],"Experimental":[70],"results":[71],"have":[72],"shown":[73],"our":[75],"proposed":[76],"flow":[78],"designs":[82],"ranging":[83],"from":[84],"100":[85],"MHz":[86,89],"300":[88],"on":[90],"fly.":[92]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
