{"id":"https://openalex.org/W2145146769","doi":"https://doi.org/10.1109/iscas.2002.1010467","title":"Efficient digit-serial FIR filters with skew-tolerant domino","display_name":"Efficient digit-serial FIR filters with skew-tolerant domino","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2145146769","doi":"https://doi.org/10.1109/iscas.2002.1010467","mag":"2145146769"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1010467","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010467","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100704329","display_name":"Sung\u2010Wook Kim","orcid":"https://orcid.org/0000-0002-5537-4793"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sungwook Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","[Dept. of Electr. & Comput. Eng., Minnesota Univ., minneapolis, MN, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Minnesota Univ., minneapolis, MN, USA]","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041064476","display_name":"Gerald E. Sobelman","orcid":"https://orcid.org/0000-0002-4415-7320"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G.E. Sobelman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","[Dept. of Electr. & Comput. Eng., Minnesota Univ., minneapolis, MN, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Minnesota Univ., minneapolis, MN, USA]","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130238516"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.31462569,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":null,"first_page":"IV","last_page":"369"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.7555786967277527},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7172983884811401},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7131850719451904},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.697528600692749},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4632808566093445},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.44444090127944946},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.4430355727672577},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3817555904388428},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3615421652793884},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22767135500907898},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.22314023971557617}],"concepts":[{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.7555786967277527},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7172983884811401},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7131850719451904},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.697528600692749},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4632808566093445},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.44444090127944946},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.4430355727672577},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3817555904388428},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3615421652793884},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22767135500907898},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.22314023971557617},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2002.1010467","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010467","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.15.1478","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.15.1478","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www-mount.ee.umn.edu/~sobelman/papers/skim_fir_iscas02.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1758921388","https://openalex.org/W1877569080","https://openalex.org/W1989859908","https://openalex.org/W2074270000","https://openalex.org/W2096336708","https://openalex.org/W2126970857","https://openalex.org/W2134440875","https://openalex.org/W2134897836","https://openalex.org/W2159868837","https://openalex.org/W2533387467","https://openalex.org/W6637890557","https://openalex.org/W7014523335"],"related_works":["https://openalex.org/W4232019485","https://openalex.org/W2028052815","https://openalex.org/W2076413498","https://openalex.org/W2164834710","https://openalex.org/W4327499872","https://openalex.org/W2116259070","https://openalex.org/W2123512677","https://openalex.org/W2128528443","https://openalex.org/W2097706495","https://openalex.org/W2066822161"],"abstract_inverted_index":{"A":[0],"novel":[1],"connection":[2],"between":[3],"digit-serial":[4,84],"computation":[5],"and":[6,74],"skew-tolerant":[7,68,89],"domino":[8,69,90,101],"circuit":[9],"design":[10],"is":[11,31,59,91],"exploited":[12],"to":[13,61,93],"create":[14],"very":[15],"efficient":[16,75],"implementations":[17],"of":[18,28,67],"FIR":[19,85],"digital":[20],"filters.":[21],"In":[22,53],"our":[23],"approach,":[24],"a":[25,41,55],"digit":[26],"size":[27],"N":[29,44],"bits":[30,45],"mapped":[32],"onto":[33],"an":[34,72,82],"N-phase":[35],"overlapping":[36],"clocking":[37],"scheme":[38],"in":[39,48,71],"such":[40],"way":[42],"that":[43,81],"are":[46],"processed":[47],"each":[49],"full":[50],"clock":[51],"cycle.":[52],"addition,":[54],"VHDL-based":[56],"verification":[57],"strategy":[58],"used":[60],"capture":[62],"the":[63],"essential":[64],"time-borrowing":[65],"behavior":[66],"circuits":[70],"accurate":[73],"manner.":[76],"The":[77],"simulation":[78],"results":[79],"show":[80],"8-tap":[83],"filter":[86],"constructed":[87],"with":[88],"up":[92],"36%":[94],"faster":[95],"than":[96],"one":[97],"built":[98],"using":[99],"traditional":[100],"circuits.":[102]},"counts_by_year":[],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2025-10-10T00:00:00"}