{"id":"https://openalex.org/W2114370929","doi":"https://doi.org/10.1109/iscas.2002.1010451","title":"Design rewiring for power minimization [logic design]","display_name":"Design rewiring for power minimization [logic design]","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2114370929","doi":"https://doi.org/10.1109/iscas.2002.1010451","mag":"2114370929"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1010451","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010451","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068977936","display_name":"Moslem Amiri","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"M. Amiri","raw_affiliation_strings":["Department ECE, University of Toronto, Toronto, ONT, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department ECE, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009841786","display_name":"Andreas Veneris","orcid":"https://orcid.org/0000-0002-6309-8821"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"A. Veneris","raw_affiliation_strings":["Department ECE and CS, University of Toronto, Toronto, ONT, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department ECE and CS, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059339979","display_name":"I. Ting","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"I. Ting","raw_affiliation_strings":["Alcatel Canada, Inc., Burnaby, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Alcatel Canada, Inc., Burnaby, BC, Canada","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4308,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.6056417,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"4","issue":null,"first_page":"IV","last_page":"305"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6597522497177124},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.6594905853271484},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.6573648452758789},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6526581645011902},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.643722414970398},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6137650012969971},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5976321697235107},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.5831922292709351},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5674017667770386},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5093632936477661},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4384256899356842},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4365882873535156},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.39607569575309753},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.2564873695373535},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.23441538214683533},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19118386507034302},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18866199254989624}],"concepts":[{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6597522497177124},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.6594905853271484},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.6573648452758789},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6526581645011902},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.643722414970398},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6137650012969971},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5976321697235107},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5831922292709351},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5674017667770386},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5093632936477661},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4384256899356842},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4365882873535156},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.39607569575309753},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2564873695373535},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.23441538214683533},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19118386507034302},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18866199254989624},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2002.1010451","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010451","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1879281873","https://openalex.org/W2006414349","https://openalex.org/W2096541971","https://openalex.org/W2102666576","https://openalex.org/W2125829999","https://openalex.org/W2127735256","https://openalex.org/W2148596540","https://openalex.org/W2149107969","https://openalex.org/W2164897963","https://openalex.org/W4232376560","https://openalex.org/W6651991523","https://openalex.org/W6665042886","https://openalex.org/W6681920825"],"related_works":["https://openalex.org/W2386022279","https://openalex.org/W1939541994","https://openalex.org/W573124066","https://openalex.org/W573531811","https://openalex.org/W818963952","https://openalex.org/W2499931839","https://openalex.org/W2110968362","https://openalex.org/W4390345338","https://openalex.org/W2071237164","https://openalex.org/W2066871890"],"abstract_inverted_index":{"A":[0],"new":[1],"ATPG-based":[2],"approach":[3],"to":[4],"multi-level":[5],"combinational":[6],"logic":[7,39],"circuit":[8],"power":[9],"optimization":[10,30],"is":[11,35,46],"presented.":[12],"This":[13],"method":[14],"borrows":[15],"from":[16],"existing":[17],"simulation-based":[18],"design":[19,33,51],"error":[20,34],"diagnosis":[21],"and":[22,44,65],"correction":[23],"techniques.":[24],"At":[25],"every":[26],"step":[27],"of":[28,67],"the":[29,50,62],"procedure,":[31],"a":[32,53],"introduced":[36],"by":[37,48],"removing":[38],"with":[40],"high":[41],"switching":[42],"activity":[43],"it":[45],"corrected":[47],"modifying":[49],"in":[52],"less":[54],"critical":[55],"area.":[56],"The":[57],"experiments":[58],"presented":[59],"here":[60],"indicate":[61],"added":[63],"flexibility":[64],"potential":[66],"this":[68],"approach.":[69]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}