{"id":"https://openalex.org/W1790411776","doi":"https://doi.org/10.1109/iscas.2002.1010428","title":"Design of a pipelined and expandable sorting architecture with simple control scheme","display_name":"Design of a pipelined and expandable sorting architecture with simple control scheme","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1790411776","doi":"https://doi.org/10.1109/iscas.2002.1010428","mag":"1790411776"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1010428","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010428","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111657990","display_name":"Chi-Sheng Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chi-Sheng Lin","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","[Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan]","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111735255","display_name":"B.-D. Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Bin-Da Liu","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","[Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan]","institution_ids":["https://openalex.org/I91807558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I91807558"],"apc_list":null,"apc_paid":null,"fwci":0.2554,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.47579804,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"4","issue":null,"first_page":"IV","last_page":"217"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7601569890975952},{"id":"https://openalex.org/keywords/sorting","display_name":"Sorting","score":0.6902749538421631},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6205627918243408},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.48932307958602905},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.48249173164367676},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4729618430137634},{"id":"https://openalex.org/keywords/sorting-network","display_name":"Sorting network","score":0.47093716263771057},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4637598991394043},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.43340739607810974},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4186832308769226},{"id":"https://openalex.org/keywords/sorting-algorithm","display_name":"Sorting algorithm","score":0.4185272455215454},{"id":"https://openalex.org/keywords/sort","display_name":"sort","score":0.41147226095199585},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40756019949913025},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37000396847724915},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.21953335404396057},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18872329592704773},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10560452938079834}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7601569890975952},{"id":"https://openalex.org/C111696304","wikidata":"https://www.wikidata.org/wiki/Q2303697","display_name":"Sorting","level":2,"score":0.6902749538421631},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6205627918243408},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.48932307958602905},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.48249173164367676},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4729618430137634},{"id":"https://openalex.org/C64540648","wikidata":"https://www.wikidata.org/wiki/Q646477","display_name":"Sorting network","level":4,"score":0.47093716263771057},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4637598991394043},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.43340739607810974},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4186832308769226},{"id":"https://openalex.org/C108094655","wikidata":"https://www.wikidata.org/wiki/Q181593","display_name":"Sorting algorithm","level":3,"score":0.4185272455215454},{"id":"https://openalex.org/C88548561","wikidata":"https://www.wikidata.org/wiki/Q347599","display_name":"sort","level":2,"score":0.41147226095199585},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40756019949913025},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37000396847724915},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.21953335404396057},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18872329592704773},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10560452938079834},{"id":"https://openalex.org/C23123220","wikidata":"https://www.wikidata.org/wiki/Q816826","display_name":"Information retrieval","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2002.1010428","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010428","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7900000214576721}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1877305132","https://openalex.org/W2006097283","https://openalex.org/W2075220256","https://openalex.org/W2104301300","https://openalex.org/W2122699098","https://openalex.org/W2131956217","https://openalex.org/W2132808830","https://openalex.org/W2142869012","https://openalex.org/W2154165887","https://openalex.org/W2161830806"],"related_works":["https://openalex.org/W2085265870","https://openalex.org/W2396743875","https://openalex.org/W2362374543","https://openalex.org/W2094179388","https://openalex.org/W2126436988","https://openalex.org/W2325315917","https://openalex.org/W2372558933","https://openalex.org/W2348196682","https://openalex.org/W2385397541","https://openalex.org/W4239051739"],"abstract_inverted_index":{"This":[0,21,108],"paper":[1],"presents":[2],"a":[3,19,26,67],"novel":[4],"circuit":[5],"for":[6,112],"the":[7,90,98],"pipelined":[8],"and":[9,57,69],"expandable":[10],"sorting":[11,36,39],"architecture":[12,40,53],"that":[13,89],"processes":[14],"thirty-two":[15],"16-bit":[16],"patterns":[17],"at":[18],"time.":[20],"design":[22,75,109],"is":[23,110],"based":[24],"on":[25],"compare-swap":[27],"cell":[28],"which":[29],"can":[30,62,92,116],"easily":[31],"be":[32,63,118],"cascaded":[33],"to":[34,44,65,95],"improve":[35],"performance.":[37],"The":[38,50,73,85],"combines":[41],"suitable":[42,111],"algorithm":[43],"sort":[45],"arbitrary":[46],"N":[47],"data":[48],"patterns.":[49],"proposed":[51],"hardware":[52,71],"features":[54],"layout":[55],"regularity":[56],"interconnection":[58],"compactness,":[59],"thus":[60],"it":[61],"exploited":[64],"obtain":[66],"small":[68],"efficient":[70],"implementation.":[72,114],"whole":[74],"was":[76],"fabricated":[77],"by":[78],"TSMC":[79],"0.35/spl":[80],"mu/m":[81],"SPQM":[82],"CMOS":[83],"process.":[84],"estimation":[86],"results":[87],"indicate":[88],"sorter":[91],"work":[93],"up":[94],"66MHz":[96],"with":[97],"power":[99],"consumption":[100],"less":[101],"than":[102],"20mW":[103],"under":[104],"3.3V":[105],"supply":[106],"voltage.":[107],"VLSI":[113],"It":[115],"also":[117],"applied":[119],"well":[120],"when":[121],"being":[122],"embedded":[123],"in":[124],"digital":[125],"signal":[126],"processors.":[127]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
