{"id":"https://openalex.org/W1556453147","doi":"https://doi.org/10.1109/iscas.2002.1010426","title":"A scalable sorting architecture based on maskable WTA/MAX circuit","display_name":"A scalable sorting architecture based on maskable WTA/MAX circuit","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1556453147","doi":"https://doi.org/10.1109/iscas.2002.1010426","mag":"1556453147"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1010426","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010426","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057013202","display_name":"Shin-Hong Ou","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shin-Hong Ou","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","[Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan]","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111657990","display_name":"Chi-Sheng Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chi-Sheng Lin","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","[Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan]","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051419622","display_name":"Bin-Da Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Bin-Da Liu","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","[Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan]","institution_ids":["https://openalex.org/I91807558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I91807558"],"apc_list":null,"apc_paid":null,"fwci":0.8615,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.68543366,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"4","issue":null,"first_page":"IV","last_page":"209"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sorting","display_name":"Sorting","score":0.8291051983833313},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7531325817108154},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.6061064600944519},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5977780222892761},{"id":"https://openalex.org/keywords/sorting-network","display_name":"Sorting network","score":0.589871883392334},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5060490965843201},{"id":"https://openalex.org/keywords/sort","display_name":"sort","score":0.4982011318206787},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4865952730178833},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.43754303455352783},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4145032465457916},{"id":"https://openalex.org/keywords/sorting-algorithm","display_name":"Sorting algorithm","score":0.3738778531551361},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1280106008052826}],"concepts":[{"id":"https://openalex.org/C111696304","wikidata":"https://www.wikidata.org/wiki/Q2303697","display_name":"Sorting","level":2,"score":0.8291051983833313},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7531325817108154},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.6061064600944519},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5977780222892761},{"id":"https://openalex.org/C64540648","wikidata":"https://www.wikidata.org/wiki/Q646477","display_name":"Sorting network","level":4,"score":0.589871883392334},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5060490965843201},{"id":"https://openalex.org/C88548561","wikidata":"https://www.wikidata.org/wiki/Q347599","display_name":"sort","level":2,"score":0.4982011318206787},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4865952730178833},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.43754303455352783},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4145032465457916},{"id":"https://openalex.org/C108094655","wikidata":"https://www.wikidata.org/wiki/Q181593","display_name":"Sorting algorithm","level":3,"score":0.3738778531551361},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1280106008052826},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C23123220","wikidata":"https://www.wikidata.org/wiki/Q816826","display_name":"Information retrieval","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2002.1010426","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010426","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6800000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1918947868","https://openalex.org/W2006097283","https://openalex.org/W2096496118","https://openalex.org/W2111391058","https://openalex.org/W2122685942","https://openalex.org/W2132808830","https://openalex.org/W2137138983","https://openalex.org/W2139081844","https://openalex.org/W2142869012","https://openalex.org/W2154165887","https://openalex.org/W2155816520","https://openalex.org/W6640252689"],"related_works":["https://openalex.org/W2085265870","https://openalex.org/W2396743875","https://openalex.org/W2362374543","https://openalex.org/W2094179388","https://openalex.org/W2126436988","https://openalex.org/W2325315917","https://openalex.org/W2372558933","https://openalex.org/W2348196682","https://openalex.org/W2385397541","https://openalex.org/W4239051739"],"abstract_inverted_index":{"Sorting":[0],"plays":[1],"an":[2,32,77],"important":[3],"role":[4],"in":[5],"data":[6,37,52],"and":[7,91],"digital":[8],"signal/image":[9],"processing.":[10],"We":[11,75],"propose":[12],"a":[13,19,39,71,99,122,130],"sorter":[14,27,79,106,116],"system":[15,65],"architecture":[16],"based":[17],"upon":[18],"novel":[20],"maskable":[21],"WTA/MAX":[22],"circuit":[23,93],"design.":[24],"The":[25,115],"proposed":[26,63,84,105],"is":[28,47,89,95],"able":[29],"to":[30,81,111],"sort":[31],"arbitrary":[33],"N":[34],"items":[35],"of":[36,103],"with":[38,129],"simple":[40,72],"control":[41],"mechanism.":[42],"No":[43],"extra":[44],"memory":[45],"space":[46],"needed":[48],"for":[49],"storing":[50],"temporary":[51],"during":[53],"the":[54,62,92,101],"sorting":[55,60,64],"process.":[56],"To":[57],"achieve":[58],"higher":[59],"speed,":[61],"can":[66,107],"be":[67,108],"expanded":[68],"easily":[69,109],"by":[70,121],"hardware":[73],"cascade.":[74],"use":[76],"8-bit":[78],"design":[80],"verify":[82],"our":[83,104,138],"architecture.":[85],"A":[86],"modular":[87],"concept":[88],"adopted":[90],"interconnection":[94],"fairly":[96],"regular.":[97],"As":[98],"result,":[100],"bit-length":[102],"augmented":[110],"16-bit":[112],"or":[113],"32-bit.":[114],"chip":[117,139],"has":[118],"been":[119],"manufactured":[120],"TSMC":[123],"0.35":[124],"/spl":[125],"mu/m":[126],"1P4M":[127],"process":[128],"32":[131],"S/B":[132],"package.":[133],"Experimental":[134],"results":[135],"show":[136],"that":[137],"functions":[140],"correctly":[141],"at":[142,145],"50":[143],"MHz":[144],"3.3":[146],"V":[147],"power":[148],"supply":[149],"voltage.":[150]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}