{"id":"https://openalex.org/W1581128427","doi":"https://doi.org/10.1109/iscas.2002.1010391","title":"Memory exploration utilizing scheduling effects in high-level synthesis","display_name":"Memory exploration utilizing scheduling effects in high-level synthesis","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1581128427","doi":"https://doi.org/10.1109/iscas.2002.1010391","mag":"1581128427"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1010391","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010391","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100513387","display_name":"Jaewon Seo","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jaewon Seo","raw_affiliation_strings":["Department of Electrical Engineering & Computer Science and Advanced Information Technology Research Center, Korea Advanced Institute of Science and Technology, South Korea","Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering & Computer Science and Advanced Information Technology Research Center, Korea Advanced Institute of Science and Technology, South Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":null,"display_name":"Thewhan Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Thewhan Kim","raw_affiliation_strings":["Department of Electrical Engineering & Computer Science and Advanced Information Technology Research Center, Korea Advanced Institute of Science and Technology, South Korea","Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering & Computer Science and Advanced Information Technology Research Center, Korea Advanced Institute of Science and Technology, South Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I157485424"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04433498,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":null,"first_page":"IV","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7869197726249695},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5839233994483948},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5458030104637146},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.48808014392852783},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.46392378211021423},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4466288387775421},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.44280144572257996},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42925646901130676},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.41091740131378174},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3282301425933838},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3234126567840576},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22102591395378113},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1855609118938446},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.0984123945236206},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.09644410014152527},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.08259031176567078}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7869197726249695},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5839233994483948},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5458030104637146},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.48808014392852783},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.46392378211021423},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4466288387775421},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.44280144572257996},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42925646901130676},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.41091740131378174},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3282301425933838},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3234126567840576},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22102591395378113},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1855609118938446},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.0984123945236206},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.09644410014152527},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.08259031176567078},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2002.1010391","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010391","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322348","display_name":"Korea Science and Engineering Foundation","ror":"https://ror.org/013aysd81"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1994115836","https://openalex.org/W2071780990","https://openalex.org/W2107401056","https://openalex.org/W2108827214","https://openalex.org/W2128544270","https://openalex.org/W2131629224","https://openalex.org/W2136097861","https://openalex.org/W2170120409","https://openalex.org/W2542047833","https://openalex.org/W3145997180","https://openalex.org/W4232888013","https://openalex.org/W4246977621","https://openalex.org/W6676247895","https://openalex.org/W6679386228"],"related_works":["https://openalex.org/W2362277122","https://openalex.org/W2334181344","https://openalex.org/W2043352873","https://openalex.org/W2143690511","https://openalex.org/W4281569059","https://openalex.org/W2036525499","https://openalex.org/W1591576069","https://openalex.org/W1975698617","https://openalex.org/W2561005478","https://openalex.org/W1976676268"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,45],"address":[4],"one":[5],"critical":[6],"limitation":[7],"of":[8,15,25,65,75],"the":[9,13,43,54,73,76],"previous":[10],"work":[11],"on":[12,62],"problem":[14],"memory":[16,29,38,55,83],"exploration":[17,78],"in":[18,80],"high-level":[19],"synthesis,":[20],"namely,":[21],"a":[22,63],"tight":[23],"coupling":[24],"scheduling":[26],"effects":[27],"with":[28],"exploration,":[30],"that":[31,50],"has":[32],"been":[33],"ignored":[34],"by":[35],"most":[36],"existing":[37],"synthesis":[39],"systems.":[40],"To":[41],"overcome":[42],"limitation,":[44],"propose":[46],"an":[47],"integrated":[48],"approach":[49],"takes":[51],"into":[52],"account":[53],"configurations":[56],"and":[57],"schedules":[58],"simultaneously.":[59],"Experimental":[60],"data":[61],"set":[64],"benchmark":[66],"filter":[67],"designs":[68],"are":[69],"provided":[70],"to":[71],"show":[72],"effectiveness":[74],"proposed":[77],"strategy":[79],"finding":[81],"close-to-optimal":[82],"configurations.":[84]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}