{"id":"https://openalex.org/W2137881192","doi":"https://doi.org/10.1109/iscas.2002.1010185","title":"A fault tolerant incremental design methodology","display_name":"A fault tolerant incremental design methodology","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2137881192","doi":"https://doi.org/10.1109/iscas.2002.1010185","mag":"2137881192"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1010185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010185","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063423941","display_name":"S. Cailotto","orcid":null},"institutions":[{"id":"https://openalex.org/I119439378","display_name":"University of Verona","ror":"https://ror.org/039bp8j42","country_code":"IT","type":"education","lineage":["https://openalex.org/I119439378"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"S. Cailotto","raw_affiliation_strings":["Dipartimento di Informatica, Universi\u00e1 di Verona, Italy","Dipt. di Informatica, Universita di Verona, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Informatica, Universi\u00e1 di Verona, Italy","institution_ids":["https://openalex.org/I119439378"]},{"raw_affiliation_string":"Dipt. di Informatica, Universita di Verona, Italy","institution_ids":["https://openalex.org/I119439378"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037661652","display_name":"Alessandro Fin","orcid":null},"institutions":[{"id":"https://openalex.org/I119439378","display_name":"University of Verona","ror":"https://ror.org/039bp8j42","country_code":"IT","type":"education","lineage":["https://openalex.org/I119439378"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Fin","raw_affiliation_strings":["Dipartimento di Informatica, Universi\u00e1 di Verona, Italy","Dipt. di Informatica, Universita di Verona, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Informatica, Universi\u00e1 di Verona, Italy","institution_ids":["https://openalex.org/I119439378"]},{"raw_affiliation_string":"Dipt. di Informatica, Universita di Verona, Italy","institution_ids":["https://openalex.org/I119439378"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040302302","display_name":"Franco Fummi","orcid":"https://orcid.org/0000-0002-4404-5791"},"institutions":[{"id":"https://openalex.org/I119439378","display_name":"University of Verona","ror":"https://ror.org/039bp8j42","country_code":"IT","type":"education","lineage":["https://openalex.org/I119439378"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Fummi","raw_affiliation_strings":["Dipartimento di Informatica, Universi\u00e1 di Verona, Italy","Dipt. di Informatica, Universita di Verona, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Informatica, Universi\u00e1 di Verona, Italy","institution_ids":["https://openalex.org/I119439378"]},{"raw_affiliation_string":"Dipt. di Informatica, Universita di Verona, Italy","institution_ids":["https://openalex.org/I119439378"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5063423941"],"corresponding_institution_ids":["https://openalex.org/I119439378"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20321481,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":null,"first_page":"III","last_page":"161"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.763961136341095},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.5442982912063599},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4985790252685547},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.49081310629844666},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4870801270008087},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.48008567094802856},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.4794398844242096},{"id":"https://openalex.org/keywords/upgrade","display_name":"Upgrade","score":0.47366198897361755},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.4398803412914276},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3349056839942932},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.29334402084350586},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2732468247413635},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1337953805923462},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07814645767211914}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.763961136341095},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.5442982912063599},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4985790252685547},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.49081310629844666},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4870801270008087},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.48008567094802856},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.4794398844242096},{"id":"https://openalex.org/C2780615140","wikidata":"https://www.wikidata.org/wiki/Q920419","display_name":"Upgrade","level":2,"score":0.47366198897361755},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.4398803412914276},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3349056839942932},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.29334402084350586},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2732468247413635},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1337953805923462},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07814645767211914},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2002.1010185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010185","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/10","score":0.5799999833106995,"display_name":"Reduced inequalities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2060461359","https://openalex.org/W2072159791","https://openalex.org/W2081466287","https://openalex.org/W2095852602","https://openalex.org/W2099120582","https://openalex.org/W2110382043","https://openalex.org/W2145401040","https://openalex.org/W2150886090","https://openalex.org/W2158246429"],"related_works":["https://openalex.org/W2368672678","https://openalex.org/W2370626080","https://openalex.org/W2368576029","https://openalex.org/W2377210208","https://openalex.org/W116478885","https://openalex.org/W2391279445","https://openalex.org/W2051543817","https://openalex.org/W2390420166","https://openalex.org/W2354998446","https://openalex.org/W2232520249"],"abstract_inverted_index":{"Incremental":[0],"design":[1,9,78,125],"is":[2,48],"the":[3,19,35,51,77,80,94,97,107],"widest":[4],"applied":[5,88],"methodology":[6,126],"for":[7],"VLSI":[8],"since,":[10],"it":[11],"allows":[12],"one":[13,29,47],"to":[14,30,43,73,128],"produce":[15],"early":[16],"versions":[17],"of":[18,53,83],"system":[20,41],"that,":[21],"even":[22],"if":[23],"not":[24],"satisfying":[25],"all":[26],"requirements,":[27],"allow":[28],"verify":[31],"its":[32],"applicability":[33],"in":[34,89],"field.":[36],"The":[37,114],"migration":[38],"from,":[39],"a":[40,44,54,57,121],"version":[42],"more":[45,58],"powerful":[46,59],"based":[49],"on":[50],"substitution":[52],"module":[55,99],"with":[56],"module,":[60],"which":[61,70],"implements":[62],"new":[63],"features.":[64],"This":[65],"upgrade":[66],"can":[67,100,105],"introduce":[68],"errors,":[69],"are":[71],"difficult":[72],"be":[74,87],"identified":[75],"during":[76],"since":[79],"standard":[81],"concept":[82],"equivalence":[84],"checking":[85],"cannot":[86],"this":[90,117],"context.":[91],"In":[92],"fact,":[93],"original":[95],"and":[96,119],"redesigned":[98],"implement":[101],"different":[102,111],"specifications":[103],"or":[104,130],"achieve":[106],"same":[108],"results":[109],"under":[110],"timing":[112],"constraints.":[113],"paper":[115],"analyzes":[116],"problem":[118],"proposes":[120],"fault":[122],"tolerant":[123],"incremental":[124],"able":[127],"reduce":[129],"avoid":[131],"such":[132],"errors.":[133]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}