{"id":"https://openalex.org/W1953356645","doi":"https://doi.org/10.1109/iscas.2002.1009851","title":"Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits","display_name":"Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1953356645","doi":"https://doi.org/10.1109/iscas.2002.1009851","mag":"1953356645"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1009851","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1009851","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057502977","display_name":"Roy Mader","orcid":null},"institutions":[{"id":"https://openalex.org/I4210134769","display_name":"University of Pittsburgh Medical Center","ror":"https://ror.org/04ehecz88","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210098814","https://openalex.org/I4210134769"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Mader","raw_affiliation_strings":["Department of Electrical Engineering, University of Pittsburgh Medical Center, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Pittsburgh Medical Center, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I4210134769"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053517349","display_name":"Eby G. Friedman","orcid":"https://orcid.org/0000-0002-5549-7160"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"E.G. Friedman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109163662","display_name":"Ami Litman","orcid":null},"institutions":[{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"A. Litman","raw_affiliation_strings":["Department of Computer Science, Technion-Israel Institute of Technology, Haifa, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Technion-Israel Institute of Technology, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070703425","display_name":"Ivan S. Kourtev","orcid":null},"institutions":[{"id":"https://openalex.org/I4210134769","display_name":"University of Pittsburgh Medical Center","ror":"https://ror.org/04ehecz88","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210098814","https://openalex.org/I4210134769"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"I.S. Kourtev","raw_affiliation_strings":["Department of Electrical Engineering, University of Pittsburgh Medical Center, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Pittsburgh Medical Center, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I4210134769"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3543,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.61057696,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"I","last_page":"357"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.842650294303894},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.7699562311172485},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.671607494354248},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6613423824310303},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6605101227760315},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.5901244878768921},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5601856708526611},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5286980867385864},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5067976117134094},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.49190521240234375},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.47883060574531555},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.30962657928466797},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2214980125427246},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19822707772254944},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.19350504875183105}],"concepts":[{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.842650294303894},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.7699562311172485},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.671607494354248},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6613423824310303},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6605101227760315},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.5901244878768921},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5601856708526611},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5286980867385864},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5067976117134094},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.49190521240234375},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.47883060574531555},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.30962657928466797},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2214980125427246},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19822707772254944},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.19350504875183105},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2002.1009851","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1009851","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.15.1320","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.15.1320","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.rochester.edu:8080/users/friedman/papers/ISCAS_02_Clockscheduling.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W638906082","https://openalex.org/W1501367650","https://openalex.org/W1502296014","https://openalex.org/W1864700546","https://openalex.org/W1875554762","https://openalex.org/W2011778848","https://openalex.org/W2056496431","https://openalex.org/W2093660707","https://openalex.org/W6630036590","https://openalex.org/W6664254336"],"related_works":["https://openalex.org/W4247180033","https://openalex.org/W2088914741","https://openalex.org/W2559451387","https://openalex.org/W2040807843","https://openalex.org/W4249038728","https://openalex.org/W2148462217","https://openalex.org/W3006003651","https://openalex.org/W2144282137","https://openalex.org/W1999924508","https://openalex.org/W2117814846"],"abstract_inverted_index":{"This":[0,41],"paper":[1],"compares":[2],"several":[3],"methods":[4],"for":[5,13],"determining":[6],"an":[7,54],"optimal":[8],"non-zero":[9],"clock":[10,23,51,57,70],"skew":[11,24,71],"schedule":[12,25,52],"synchronous":[14],"digital":[15],"VLSI":[16],"circuits.":[17,93],"The":[18],"optimality":[19,42],"of":[20,37,48,68,91],"a":[21,77],"given":[22],"which":[26],"satisfies":[27],"the":[28,35,46,49,69,88,100],"circuit":[29,38],"timing":[30,39],"constraints":[31],"is":[32,43,81],"defined":[33],"from":[34,53],"perspective":[36],"reliability.":[40],"characterized":[44],"by":[45],"deviation":[47],"computed":[50],"'ideal'":[55],"objective":[56],"schedule.":[58],"Both":[59],"linear":[60],"and":[61,65,76],"quadratic":[62],"programming":[63],"(LP":[64],"QP)":[66],"formulations":[67,84],"scheduling":[72],"problem":[73],"are":[74,85,97],"analyzed":[75],"novel":[78],"LP":[79],"formulation":[80],"introduced.":[82],"These":[83],"compared":[86],"using":[87,99],"ISCAS'89":[89],"suite":[90],"benchmark":[92],"Mathematical":[94],"optimization":[95,103],"results":[96],"calculated":[98],"large":[101],"scale":[102],"package":[104],"Lancelot.":[105]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
