{"id":"https://openalex.org/W4250281317","doi":"https://doi.org/10.1109/isca.2014.6853222","title":"Memory persistency","display_name":"Memory persistency","publication_year":2014,"publication_date":"2014-06-01","ids":{"openalex":"https://openalex.org/W4250281317","doi":"https://doi.org/10.1109/isca.2014.6853222"},"language":"en","primary_location":{"id":"doi:10.1109/isca.2014.6853222","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2014.6853222","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053454549","display_name":"Steven Pelley","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Steven Pelley","raw_affiliation_strings":["University of Michigan"],"affiliations":[{"raw_affiliation_string":"University of Michigan","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027819880","display_name":"Peter M. Chen","orcid":"https://orcid.org/0000-0002-5951-4183"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter M. Chen","raw_affiliation_strings":["University of Michigan"],"affiliations":[{"raw_affiliation_string":"University of Michigan","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018949021","display_name":"Thomas F. Wenisch","orcid":"https://orcid.org/0000-0001-9560-2124"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Thomas F. Wenisch","raw_affiliation_strings":["University of Michigan"],"affiliations":[{"raw_affiliation_string":"University of Michigan","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5053454549"],"corresponding_institution_ids":["https://openalex.org/I27837315"],"apc_list":null,"apc_paid":null,"fwci":16.8563,"has_fulltext":false,"cited_by_count":130,"citation_normalized_percentile":{"value":0.99512152,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"265","last_page":"276"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.8532028198242188},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7876442670822144},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.5701866745948792},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.5569804310798645},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.5314565896987915},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49826979637145996},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.4391992688179016},{"id":"https://openalex.org/keywords/consistency","display_name":"Consistency (knowledge bases)","score":0.4349656403064728},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.4287336468696594},{"id":"https://openalex.org/keywords/memory-model","display_name":"Memory model","score":0.42713722586631775},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42607763409614563},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.34920692443847656},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3487713932991028},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3476145267486572},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.3251489996910095},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.3010396957397461},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24889150261878967},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14093893766403198}],"concepts":[{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.8532028198242188},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7876442670822144},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.5701866745948792},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.5569804310798645},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.5314565896987915},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49826979637145996},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.4391992688179016},{"id":"https://openalex.org/C2776436953","wikidata":"https://www.wikidata.org/wiki/Q5163215","display_name":"Consistency (knowledge bases)","level":2,"score":0.4349656403064728},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.4287336468696594},{"id":"https://openalex.org/C12186640","wikidata":"https://www.wikidata.org/wiki/Q6815743","display_name":"Memory model","level":3,"score":0.42713722586631775},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42607763409614563},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.34920692443847656},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3487713932991028},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3476145267486572},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.3251489996910095},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.3010396957397461},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24889150261878967},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14093893766403198},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isca.2014.6853222","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2014.6853222","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1885534640","https://openalex.org/W1966151719","https://openalex.org/W2001738739","https://openalex.org/W2005887179","https://openalex.org/W2009404871","https://openalex.org/W2029601347","https://openalex.org/W2070761976","https://openalex.org/W2090249619","https://openalex.org/W2102449048","https://openalex.org/W2104954161","https://openalex.org/W2105271931","https://openalex.org/W2105900173","https://openalex.org/W2112753327","https://openalex.org/W2113637091","https://openalex.org/W2121795083","https://openalex.org/W2138664028","https://openalex.org/W2142101409","https://openalex.org/W2168968494","https://openalex.org/W2180095311","https://openalex.org/W3145847625","https://openalex.org/W3178148377","https://openalex.org/W4205650240","https://openalex.org/W4230076379","https://openalex.org/W4239813889","https://openalex.org/W6639236566","https://openalex.org/W6685606741"],"related_works":["https://openalex.org/W4285257158","https://openalex.org/W2185519377","https://openalex.org/W2898989424","https://openalex.org/W4293159259","https://openalex.org/W2171888576","https://openalex.org/W1494152240","https://openalex.org/W919907138","https://openalex.org/W2087924605","https://openalex.org/W1697439211","https://openalex.org/W2505369450"],"abstract_inverted_index":{"Emerging":[0],"nonvolatile":[1],"memory":[2,35,55,58,64,72,87,95,99,103,105,120,128,135],"technologies":[3],"(NVRAM)":[4],"promise":[5],"the":[6,11,61,76,116],"performance":[7,45],"of":[8,13,119,150],"DRAM":[9],"with":[10,81],"persistence":[12],"disk.":[14],"However,":[15],"constraining":[16],"NVRAM":[17,26,144,167],"write":[18,27,40,145,168],"order,":[19],"necessary":[20],"to":[21,37,83,92,102,111,142],"ensure":[22],"recovery":[23],"correctness,":[24],"limits":[25],"concurrency":[28,48,146],"and":[29,42,46,122,138],"degrades":[30],"throughput.":[31],"We":[32,85,114],"require":[33],"new":[34,90],"interfaces":[36],"minimally":[38],"describe":[39,115],"constraints":[41],"allow":[43],"high":[44,47],"data":[49],"structures.":[50],"These":[51],"goals":[52],"strongly":[53],"resemble":[54],"consistency.":[56,100],"Whereas":[57],"consistency":[59],"concerns":[60],"order":[62,77],"that":[63,78,125,157],"operations":[65],"are":[66],"observed":[67],"between":[68],"numerous":[69],"processors,":[70],"persistent":[71,94,152],"systems":[73],"must":[74],"constrain":[75],"writes":[79],"occur":[80],"respect":[82],"failure.":[84],"introduce":[86,133],"persistency,":[88],"a":[89,127,151],"approach":[91],"designing":[93],"interfaces,":[96],"building":[97],"on":[98],"Similar":[101],"consistency,":[104],"persistency":[106,121,136,159],"models":[107,137,160],"may":[108],"be":[109],"relaxed":[110,158],"improve":[112],"performance.":[113],"design":[117],"space":[118],"desirable":[123],"features":[124],"such":[126],"system":[129,162],"requires.":[130],"Finally,":[131],"we":[132],"several":[134],"evaluate":[139],"their":[140],"ability":[141],"expose":[143],"using":[147],"two":[148],"implementations":[149],"queue.":[153],"Our":[154],"results":[155],"show":[156],"accelerate":[161],"throughput":[163],"30-fold":[164],"by":[165],"reducing":[166],"constraints.":[169]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":10},{"year":2020,"cited_by_count":14},{"year":2019,"cited_by_count":11},{"year":2018,"cited_by_count":17},{"year":2017,"cited_by_count":25},{"year":2016,"cited_by_count":17},{"year":2015,"cited_by_count":11},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2022-05-12T00:00:00"}