{"id":"https://openalex.org/W4248354565","doi":"https://doi.org/10.1109/isca.2003.1207007","title":"Dynamically managing the communication-parallelism trade-off in future clustered processors","display_name":"Dynamically managing the communication-parallelism trade-off in future clustered processors","publication_year":2004,"publication_date":"2004-03-22","ids":{"openalex":"https://openalex.org/W4248354565","doi":"https://doi.org/10.1109/isca.2003.1207007"},"language":"en","primary_location":{"id":"doi:10.1109/isca.2003.1207007","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2003.1207007","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"30th Annual International Symposium on Computer Architecture, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087056095","display_name":"Rajeev Balasubramonian","orcid":"https://orcid.org/0009-0009-4093-5904"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajeev Balasubramonian","raw_affiliation_strings":["Department of Computer Science, University of Rochester, Rochester, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013232946","display_name":"Sandhya Dwarkadas","orcid":"https://orcid.org/0000-0003-2631-8191"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sandhya Dwarkadas","raw_affiliation_strings":["Department of Computer Science, University of Rochester, Rochester, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009386140","display_name":"David H. Albonesi","orcid":null},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.H. Albonesi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I5388228"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8151307702064514},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7955583333969116},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7140897512435913},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.6477980017662048},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6194487810134888},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.6173175573348999},{"id":"https://openalex.org/keywords/task-parallelism","display_name":"Task parallelism","score":0.5597624778747559},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4510762095451355},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.44904956221580505},{"id":"https://openalex.org/keywords/data-parallelism","display_name":"Data parallelism","score":0.4410618841648102},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.341180682182312},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3063505291938782},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06959858536720276},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0683557391166687}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8151307702064514},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7955583333969116},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7140897512435913},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.6477980017662048},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6194487810134888},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.6173175573348999},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.5597624778747559},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4510762095451355},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.44904956221580505},{"id":"https://openalex.org/C61483411","wikidata":"https://www.wikidata.org/wiki/Q3124522","display_name":"Data parallelism","level":3,"score":0.4410618841648102},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.341180682182312},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3063505291938782},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06959858536720276},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0683557391166687},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isca.2003.1207007","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2003.1207007","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"30th Annual International Symposium on Computer Architecture, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":42,"referenced_works":["https://openalex.org/W150323568","https://openalex.org/W1535719934","https://openalex.org/W1580623006","https://openalex.org/W1608995421","https://openalex.org/W2058930506","https://openalex.org/W2084451631","https://openalex.org/W2095587895","https://openalex.org/W2112324761","https://openalex.org/W2116758648","https://openalex.org/W2117285153","https://openalex.org/W2122939826","https://openalex.org/W2130838728","https://openalex.org/W2132148829","https://openalex.org/W2133181071","https://openalex.org/W2138351227","https://openalex.org/W2140200206","https://openalex.org/W2140460036","https://openalex.org/W2154512574","https://openalex.org/W2154702295","https://openalex.org/W2158561130","https://openalex.org/W2161991038","https://openalex.org/W2296006986","https://openalex.org/W3010145113","https://openalex.org/W3142147837","https://openalex.org/W4236258190","https://openalex.org/W4242630332","https://openalex.org/W4245631385","https://openalex.org/W4245971498","https://openalex.org/W4251468890","https://openalex.org/W4251852027","https://openalex.org/W4252737912","https://openalex.org/W4253011005","https://openalex.org/W4253546582","https://openalex.org/W4255264411","https://openalex.org/W6606148001","https://openalex.org/W6632149564","https://openalex.org/W6636146310","https://openalex.org/W6665426127","https://openalex.org/W6666882340","https://openalex.org/W6677504465","https://openalex.org/W6683418528","https://openalex.org/W6817363484"],"related_works":["https://openalex.org/W2950520577","https://openalex.org/W2003935582","https://openalex.org/W74409296","https://openalex.org/W1991844655","https://openalex.org/W2105992728","https://openalex.org/W1229628","https://openalex.org/W2009213655","https://openalex.org/W2494130044","https://openalex.org/W2593878938","https://openalex.org/W305742777"],"abstract_inverted_index":{"Clustered":[0],"microarchitectures":[1],"are":[2],"an":[3,32,117,156],"attractive":[4],"alternative":[5],"to":[6,12,89,98,159],"large":[7],"monolithic":[8],"superscalar":[9],"designs":[10],"due":[11],"their":[13],"potential":[14],"for":[15,83],"higher":[16],"clock":[17],"rates":[18],"in":[19,34,166],"the":[20,35,48,65,77,87,90,101,124,133,160,167,171],"face":[21],"of":[22,37,44,64,67,76,135,148,170],"increasingly":[23],"wire-delay-constrained":[24],"process":[25],"technologies.":[26],"As":[27,61],"increasing":[28],"transistor":[29],"counts":[30],"allow":[31],"increase":[33],"number":[36],"clusters,":[38],"thereby":[39],"allowing":[40],"more":[41],"aggressive":[42],"use":[43,94,134],"instruction-level":[45],"parallelism":[46,163],"(ILP),":[47],"inter-cluster":[49],"communication":[50,71,161],"increases":[51],"as":[52],"data":[53],"values":[54],"get":[55],"spread":[56],"across":[57],"a":[58,62,74,95],"wider":[59],"area.":[60],"result":[63],"emergence":[66],"this":[68],"trade-off":[69,164],"between":[70],"and":[72,138,162],"parallelism,":[73],"subset":[75],"total":[78],"on-chip":[79],"clusters":[80],"is":[81,107],"optimal":[82],"performance.":[84],"To":[85],"match":[86],"hardware":[88,137],"application's":[91],"needs,":[92],"we":[93],"robust":[96],"algorithm":[97],"dynamically":[99],"tune":[100],"clustered":[102],"architecture.":[103,128],"The":[104],"algorithm,":[105],"which":[106],"based":[108],"on":[109,121],"program":[110],"metrics":[111],"gathered":[112],"at":[113,140],"periodic":[114],"intervals,":[115],"achieves":[116],"11%":[118],"performance":[119],"improvement":[120],"average":[122,146],"over":[123],"best":[125],"statically":[126],"defined":[127],"We":[129],"also":[130],"show":[131],"that":[132,153],"additional":[136],"reconfiguration":[139,154],"basic":[141],"block":[142],"boundaries":[143],"can":[144],"achieve":[145],"improvements":[147],"15%.":[149],"Our":[150],"results":[151],"demonstrate":[152],"provides":[155],"effective":[157],"solution":[158],"inherent":[165],"communication-bound":[168],"processors":[169],"future.":[172]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
