{"id":"https://openalex.org/W4246784443","doi":"https://doi.org/10.1109/isca.2003.1207005","title":"Cyclone: a broadcast-free dynamic instruction scheduler with selective replay","display_name":"Cyclone: a broadcast-free dynamic instruction scheduler with selective replay","publication_year":2004,"publication_date":"2004-03-22","ids":{"openalex":"https://openalex.org/W4246784443","doi":"https://doi.org/10.1109/isca.2003.1207005"},"language":"en","primary_location":{"id":"doi:10.1109/isca.2003.1207005","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2003.1207005","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"30th Annual International Symposium on Computer Architecture, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067979276","display_name":"D. Ernst","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Ernst","raw_affiliation_strings":["Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, MI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062809175","display_name":"A. Hamel","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Hamel","raw_affiliation_strings":["Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, MI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005150309","display_name":"T. Austin","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T. Austin","raw_affiliation_strings":["Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, MI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.795,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.74658036,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"253","last_page":"262"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8697882890701294},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6571530103683472},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.5786418914794922},{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"Out-of-order execution","score":0.5116837024688721},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4895671308040619},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.46350234746932983},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.4406088888645172},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.4259020686149597},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.41482964158058167},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.400847852230072},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3641000986099243},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.33240562677383423},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.29698508977890015},{"id":"https://openalex.org/keywords/quality-of-service","display_name":"Quality of service","score":0.25196823477745056},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.20671570301055908},{"id":"https://openalex.org/keywords/rate-monotonic-scheduling","display_name":"Rate-monotonic scheduling","score":0.12599226832389832}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8697882890701294},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6571530103683472},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.5786418914794922},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.5116837024688721},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4895671308040619},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.46350234746932983},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.4406088888645172},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.4259020686149597},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.41482964158058167},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.400847852230072},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3641000986099243},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.33240562677383423},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.29698508977890015},{"id":"https://openalex.org/C5119721","wikidata":"https://www.wikidata.org/wiki/Q220501","display_name":"Quality of service","level":2,"score":0.25196823477745056},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20671570301055908},{"id":"https://openalex.org/C127456818","wikidata":"https://www.wikidata.org/wiki/Q238879","display_name":"Rate-monotonic scheduling","level":4,"score":0.12599226832389832},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isca.2003.1207005","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2003.1207005","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"30th Annual International Symposium on Computer Architecture, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.152.3327","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.152.3327","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.toronto.edu/~moshovos/ACA05/read/cyclone.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W2021609618","https://openalex.org/W2075651377","https://openalex.org/W2101536355","https://openalex.org/W2104225326","https://openalex.org/W2107416089","https://openalex.org/W2108039095","https://openalex.org/W2112833506","https://openalex.org/W2121539621","https://openalex.org/W2125424217","https://openalex.org/W2131556574","https://openalex.org/W2131797921","https://openalex.org/W2140782438","https://openalex.org/W2148555526","https://openalex.org/W2153456949","https://openalex.org/W2160776998","https://openalex.org/W2164376452","https://openalex.org/W4233032247","https://openalex.org/W4236258190","https://openalex.org/W4240643561","https://openalex.org/W4242771098","https://openalex.org/W4244227015","https://openalex.org/W4248627918","https://openalex.org/W6679474879","https://openalex.org/W6680931953","https://openalex.org/W6684386307","https://openalex.org/W6817363484"],"related_works":["https://openalex.org/W2371266106","https://openalex.org/W2117382851","https://openalex.org/W2382449560","https://openalex.org/W2767298477","https://openalex.org/W2110432562","https://openalex.org/W2025344","https://openalex.org/W2117864619","https://openalex.org/W2090337950","https://openalex.org/W2104121286","https://openalex.org/W2152155870"],"abstract_inverted_index":{"To":[0,135],"achieve":[1],"high":[2],"instruction":[3,5,26,104,157,184],"throughput,":[4],"schedulers":[6,57,71],"must":[7],"be":[8],"capable":[9],"of":[10,53,93,116,186,196],"producing":[11],"high-quality":[12,59],"schedules":[13,60],"that":[14,61,75,89,129,173],"maximize":[15],"functional":[16],"unit":[17],"utilization":[18],"while":[19],"at":[20,50,110],"the":[21,33,51,83,91,113,117,142,178,183,193,197],"same":[22],"time":[23],"enabling":[24],"fast":[25,45],"issue":[27],"logic.":[28],"Many":[29],"solutions":[30,43],"exist":[31],"to":[32,39,160],"scheduling":[34,105],"problem,":[35],"ranging":[36],"from":[37],"compile-time":[38],"run-time":[40,63,96,111],"approaches.":[41],"Compile-time":[42],"feature":[44],"and":[46,65,138],"simple":[47,147],"hardware,":[48],"but":[49,68],"expense":[52],"conservative":[54],"schedules.":[55],"Dynamic":[56],"produce":[58],"incorporate":[62],"information":[64],"dependence":[66,140],"speculation,":[67,141],"implementing":[69],"these":[70],"requires":[72,211],"complex":[73],"circuits":[74],"can":[76,181],"slow":[77],"processor":[78,118],"clock":[79],"speeds.":[80],"We":[81,151],"present":[82],"Cyclone":[84,143,179,198],"scheduler,":[85,207],"a":[86,101,126,146,205],"novel":[87],"design":[88],"captures":[90],"benefits":[92],"both":[94],"compile-and":[95],"scheduling.":[97],"Our":[98],"approach":[99,210],"utilizes":[100],"list-based":[102],"single-pass":[103],"algorithm,":[106],"implemented":[107],"by":[108,155],"hardware":[109],"in":[112],"front":[114],"end":[115],"pipeline.":[119],"Once":[120],"scheduled,":[121],"instructions":[122,163],"are":[123],"injected":[124],"into":[125,133],"timed":[127],"queue":[128,176],"orchestrates":[130],"their":[131],"entry":[132],"execution.":[134],"accommodate":[136],"branch":[137],"load/store":[139],"scheduler":[144,180,199],"supports":[145],"selective":[148],"replay":[149],"mechanism.":[150],"implement":[152],"this":[153],"technique":[154],"overloading":[156],"register":[158],"forwarding":[159],"also":[161],"detect":[162],"dependent":[164],"on":[165],"incorrectly":[166],"scheduled":[167],"operations.":[168],"Detailed":[169],"simulation":[170],"analyses":[171],"suggest":[172],"with":[174],"sufficient":[175],"width,":[177],"rival":[182],"throughput":[185],"similarly":[187],"wide":[188],"monolithic":[189],"dynamic":[190],"schedulers.":[191],"Furthermore,":[192],"circuit":[194],"complexity":[195],"is":[200],"much":[201],"more":[202],"favorable":[203],"than":[204],"broadcast-based":[206],"as":[208],"our":[209],"no":[212],"global":[213],"control":[214],"signals.":[215]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}