{"id":"https://openalex.org/W4251500183","doi":"https://doi.org/10.1109/isca.2002.1003585","title":"Speculative dynamic vectorization","display_name":"Speculative dynamic vectorization","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W4251500183","doi":"https://doi.org/10.1109/isca.2002.1003585"},"language":"en","primary_location":{"id":"doi:10.1109/isca.2002.1003585","is_oa":false,"landing_page_url":"http://doi.org/10.1109/isca.2002.1003585","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 29th Annual International Symposium on Computer Architecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://hdl.handle.net/2117/105265","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025470435","display_name":"Alex Pajuelo","orcid":"https://orcid.org/0000-0002-5510-6860"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"A. Pajuelo","raw_affiliation_strings":["Departament d'Arquitectura de Computadors Universitat Polit\u00e8cnica de Catalunya Barcelona -Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departament d'Arquitectura de Computadors Universitat Polit\u00e8cnica de Catalunya Barcelona -Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100733331","display_name":"Antonio Gonz\u00e1lez","orcid":"https://orcid.org/0000-0002-0009-0996"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"A. Gonzalez","raw_affiliation_strings":["Departament d'Arquitectura de Computadors Universitat Polit\u00e8cnica de Catalunya Barcelona -Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departament d'Arquitectura de Computadors Universitat Polit\u00e8cnica de Catalunya Barcelona -Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020844763","display_name":"Mateo Valero","orcid":"https://orcid.org/0000-0003-2917-2482"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"M. Valero","raw_affiliation_strings":["Departament d'Arquitectura de Computadors Universitat Polit\u00e8cnica de Catalunya Barcelona -Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departament d'Arquitectura de Computadors Universitat Polit\u00e8cnica de Catalunya Barcelona -Spain","institution_ids":["https://openalex.org/I9617848"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5025470435"],"corresponding_institution_ids":["https://openalex.org/I9617848"],"apc_list":null,"apc_paid":null,"fwci":1.2387,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.81886228,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"271","last_page":"280"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8581221699714661},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.8435468673706055},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.8266962766647339},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.7569789886474609},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.6090680360794067},{"id":"https://openalex.org/keywords/vector-processor","display_name":"Vector processor","score":0.5757373571395874},{"id":"https://openalex.org/keywords/vectorization","display_name":"Vectorization (mathematics)","score":0.5486902594566345},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5422223210334778},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5391521453857422},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.4939022660255432},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.43101975321769714},{"id":"https://openalex.org/keywords/data-parallelism","display_name":"Data parallelism","score":0.4205301105976105},{"id":"https://openalex.org/keywords/scalar","display_name":"Scalar (mathematics)","score":0.4147064685821533},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.273263156414032},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.18403729796409607},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1492878794670105},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.08906686305999756},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08169257640838623}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8581221699714661},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.8435468673706055},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.8266962766647339},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.7569789886474609},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.6090680360794067},{"id":"https://openalex.org/C161824985","wikidata":"https://www.wikidata.org/wiki/Q919509","display_name":"Vector processor","level":2,"score":0.5757373571395874},{"id":"https://openalex.org/C41681595","wikidata":"https://www.wikidata.org/wiki/Q7917855","display_name":"Vectorization (mathematics)","level":2,"score":0.5486902594566345},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5422223210334778},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5391521453857422},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.4939022660255432},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.43101975321769714},{"id":"https://openalex.org/C61483411","wikidata":"https://www.wikidata.org/wiki/Q3124522","display_name":"Data parallelism","level":3,"score":0.4205301105976105},{"id":"https://openalex.org/C57691317","wikidata":"https://www.wikidata.org/wiki/Q1289248","display_name":"Scalar (mathematics)","level":2,"score":0.4147064685821533},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.273263156414032},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.18403729796409607},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1492878794670105},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.08906686305999756},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08169257640838623},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isca.2002.1003585","is_oa":false,"landing_page_url":"http://doi.org/10.1109/isca.2002.1003585","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 29th Annual International Symposium on Computer Architecture","raw_type":"proceedings-article"},{"id":"pmh:oai:upcommons.upc.edu:2117/105265","is_oa":true,"landing_page_url":"https://hdl.handle.net/2117/105265","pdf_url":null,"source":{"id":"https://openalex.org/S4377196262","display_name":"UPCommons institutional repository (Universitat Polit\u00e8cnica de Catalunya)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I9617848","host_organization_name":"Universitat Polit\u00e8cnica de Catalunya","host_organization_lineage":["https://openalex.org/I9617848"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:upcommons.upc.edu:2117/105265","is_oa":true,"landing_page_url":"https://hdl.handle.net/2117/105265","pdf_url":null,"source":{"id":"https://openalex.org/S4377196262","display_name":"UPCommons institutional repository (Universitat Polit\u00e8cnica de Catalunya)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I9617848","host_organization_name":"Universitat Polit\u00e8cnica de Catalunya","host_organization_lineage":["https://openalex.org/I9617848"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1864485850","https://openalex.org/W1984077225","https://openalex.org/W2032094184","https://openalex.org/W2037326622","https://openalex.org/W2049890071","https://openalex.org/W2069173777","https://openalex.org/W2098079396","https://openalex.org/W2118864867","https://openalex.org/W2126049154","https://openalex.org/W2135736783","https://openalex.org/W2141363922","https://openalex.org/W2144481293","https://openalex.org/W2913795363","https://openalex.org/W4234211448","https://openalex.org/W4239773716","https://openalex.org/W4242387896","https://openalex.org/W4248445118","https://openalex.org/W4249652320","https://openalex.org/W4251833217","https://openalex.org/W6659984118","https://openalex.org/W6662789940","https://openalex.org/W6678014108","https://openalex.org/W6759043259"],"related_works":["https://openalex.org/W4214860336","https://openalex.org/W2021345648","https://openalex.org/W3007272028","https://openalex.org/W2526302199","https://openalex.org/W4240606930","https://openalex.org/W983046950","https://openalex.org/W35382565","https://openalex.org/W1595834484","https://openalex.org/W2143375055","https://openalex.org/W2739502945"],"abstract_inverted_index":{"Traditional":[0],"vector":[1,88,91,118,143,219],"architectures":[2],"have":[3],"shown":[4],"to":[5,38,51,62,69,102,122,147,164,184,194],"be":[6,70,103,123],"very":[7],"effective":[8],"for":[9,31,204,208,222,226,235],"regular":[10],"codes":[11],"where":[12],"the":[13,33,130,133,138,196,211,230],"compiler":[14,34],"can":[15],"detect":[16],"data-level":[17],"parallelism.":[18],"However,":[19],"this":[20,42,79],"SIMD":[21,53],"parallelism":[22,54],"is":[23,35,61,174,191],"also":[24],"present":[25],"in":[26,49,55,86,120,155,198],"irregular":[27],"or":[28,149],"pointer-rich":[29],"codes,":[30],"which":[32],"quite":[36],"limited":[37],"discover":[39],"it.":[40],"In":[41,78],"paper":[43],"we":[44],"propose":[45],"a":[46,56,87,109,117,141,152,165],"microarchitecture":[47,161],"extension":[48,162],"order":[50,121],"exploit":[52],"speculative":[57,146],"way.":[58],"The":[59,159],"idea":[60],"predict":[63],"when":[64],"certain":[65],"operations":[66],"are":[67,84,100,114],"likely":[68],"vectorizable,":[71],"based":[72],"on":[73,94,116],"some":[74],"previous":[75],"history":[76],"information.":[77],"case,":[80],"these":[81],"scalar":[82,182,214],"instructions":[83,92,216],"executed":[85],"mode.":[89],"These":[90],"operate":[93],"several":[95],"elements":[96],"(vector":[97],"operands)":[98],"that":[99,113],"anticipated":[101],"their":[104,218],"input":[105],"operands":[106],"and":[107,206,224,228],"produce":[108],"number":[110,199],"of":[111,129,132,140,157,200,213,232],"outputs":[112],"stored":[115],"register":[119],"used":[124],"by":[125],"further":[126],"instructions.":[127],"Verification":[128],"correctness":[131],"applied":[134,163],"vectorization":[135],"eventually":[136],"changes":[137],"status":[139],"given":[142],"element":[144],"from":[145],"non-speculative,":[148],"alternatively,":[150],"generates":[151],"recovery":[153],"action":[154],"case":[156],"misspeculation.":[158],"proposed":[160],"4-way":[166],"issue":[167],"superscalar":[168],"processor":[169,179],"with":[170,180],"one":[171],"wide":[172],"bus":[173],"19%":[175],"faster":[176],"than":[177],"the,same":[178],"4":[181],"buses":[183],"Ll":[185],"data":[186],"cache.":[187],"This":[188],"speed":[189],"up":[190],"due":[192],"basically":[193],"1)":[195],"reduction":[197],"memory":[201],"accesses,":[202],"15%":[203],"SpecInt":[205,223],"20%":[207],"SpecFP,":[209,227],"2)":[210],"transformation":[212],"arithmetic":[215],"into":[217],"counterpart,":[220],"28%":[221],"23%":[225],"3)":[229],"exploitation":[231],"control":[233],"independence":[234],"mispredicted":[236],"branches.":[237]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-05-06T08:25:59.206177","created_date":"2022-05-12T00:00:00"}
