{"id":"https://openalex.org/W4253421865","doi":"https://doi.org/10.1109/isca.2002.1003558","title":"The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays","display_name":"The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W4253421865","doi":"https://doi.org/10.1109/isca.2002.1003558"},"language":"en","primary_location":{"id":"doi:10.1109/isca.2002.1003558","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2002.1003558","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 29th Annual International Symposium on Computer Architecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064155101","display_name":"M.S. Hrishikesh","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M.S. Hrishikesh","raw_affiliation_strings":["Department of Electrical and Computer Engineering","Department of Electrical and Computer Engineering, University of Texas, Austin, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering","institution_ids":[]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas, Austin, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050207942","display_name":"Norman P. Jouppi","orcid":"https://orcid.org/0000-0003-1765-1929"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N.P. Jouppi","raw_affiliation_strings":["Department of Computer Sciences, The University of Texas, Austin","Department of Computer Sciences,Western Research Laboratory, Compaq Computer Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Sciences, The University of Texas, Austin","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Department of Computer Sciences,Western Research Laboratory, Compaq Computer Corporation, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046909383","display_name":"Keith I. Farkas","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"K.I. Farkas","raw_affiliation_strings":["Western Research Lab, Compaq Computer Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Western Research Lab, Compaq Computer Corporation, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067337700","display_name":"Doug Burger","orcid":"https://orcid.org/0009-0006-6588-6596"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Burger","raw_affiliation_strings":["Department of Computer Sciences, The University of Texas, Austin"],"affiliations":[{"raw_affiliation_string":"Department of Computer Sciences, The University of Texas, Austin","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063354509","display_name":"Stephen W. Keckler","orcid":"https://orcid.org/0000-0001-6701-6099"},"institutions":[{"id":"https://openalex.org/I4210093075","display_name":"PQ Corporation (Canada)","ror":"https://ror.org/01cwhph72","country_code":"CA","type":"company","lineage":["https://openalex.org/I4210093075"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"S.W. Keckler","raw_affiliation_strings":["Western Research Lab, Compaq Computer Corporation"],"affiliations":[{"raw_affiliation_string":"Western Research Lab, Compaq Computer Corporation","institution_ids":["https://openalex.org/I4210093075"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084331444","display_name":"Premkishore Shivakumar","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Shivakumar","raw_affiliation_strings":["Department of Computer Sciences, The University of Texas, Austin","Department of Computer Sciences,Western Research Laboratory, Compaq Computer Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Sciences, The University of Texas, Austin","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Department of Computer Sciences,Western Research Laboratory, Compaq Computer Corporation, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5064155101"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":15.9952,"has_fulltext":false,"cited_by_count":91,"citation_normalized_percentile":{"value":0.99464658,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"14","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.7862635850906372},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7047383189201355},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6725835204124451},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6626184582710266},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6572428345680237},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5775851607322693},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.5377827286720276},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.48938363790512085},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.48409879207611084},{"id":"https://openalex.org/keywords/integer","display_name":"Integer (computer science)","score":0.4694862961769104},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.4632469415664673},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.4567611515522003},{"id":"https://openalex.org/keywords/window","display_name":"Window (computing)","score":0.44736576080322266},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4269799590110779},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3635268807411194},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3613603711128235},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1565801203250885},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1552802324295044},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.12198156118392944},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10658711194992065},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10493206977844238},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.09653472900390625}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.7862635850906372},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7047383189201355},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6725835204124451},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6626184582710266},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6572428345680237},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5775851607322693},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.5377827286720276},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.48938363790512085},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.48409879207611084},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.4694862961769104},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.4632469415664673},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.4567611515522003},{"id":"https://openalex.org/C2778751112","wikidata":"https://www.wikidata.org/wiki/Q835016","display_name":"Window (computing)","level":2,"score":0.44736576080322266},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4269799590110779},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3635268807411194},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3613603711128235},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1565801203250885},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1552802324295044},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.12198156118392944},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10658711194992065},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10493206977844238},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.09653472900390625},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isca.2002.1003558","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2002.1003558","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 29th Annual International Symposium on Computer Architecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5400000214576721,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W63944998","https://openalex.org/W1486900065","https://openalex.org/W1527137186","https://openalex.org/W1562342676","https://openalex.org/W1981303856","https://openalex.org/W2043687377","https://openalex.org/W2109195618","https://openalex.org/W2125092016","https://openalex.org/W2145829524","https://openalex.org/W2161864047","https://openalex.org/W2164376452","https://openalex.org/W2171825402","https://openalex.org/W2532895182","https://openalex.org/W4206262716","https://openalex.org/W4240717542","https://openalex.org/W4244330651","https://openalex.org/W6602613798","https://openalex.org/W6678503406","https://openalex.org/W6728375410"],"related_works":["https://openalex.org/W2174922170","https://openalex.org/W2116514610","https://openalex.org/W2003180247","https://openalex.org/W1487986186","https://openalex.org/W331180034","https://openalex.org/W1514283284","https://openalex.org/W2121694082","https://openalex.org/W2144518356","https://openalex.org/W1506442459","https://openalex.org/W2158864330"],"abstract_inverted_index":{"Microprocessor":[0],"clock":[1,49,77,96,124],"frequency":[2],"has":[3,15],"improved":[4],"by":[5,21,113],"nearly":[6],"40%":[7],"annually":[8],"over":[9,118],"the":[10,31,47,132],"past":[11],"decade.":[12],"This":[13],"improvement":[14],"been":[16],"provided,":[17],"in":[18,43,138],"equal":[19],"measure,":[20],"smaller":[22],"technologies":[23],"and":[24,68,95,145],"deeper":[25],"pipelines.":[26],"From":[27],"our":[28],"study":[29,100],"of":[30,62,65,71,110,116],"SPEC":[32],"2000":[33],"benchmarks,":[34,60],"we":[35,143],"find":[36,86],"that":[37,102],"for":[38,58,79],"a":[39,114,139,147,151],"high-performance":[40],"architecture":[41],"implemented":[42],"100":[44],"nm":[45],"technology,":[46],"optimal":[48,76,88],"period":[50,78],"is":[51,82],"approximately":[52],"8":[53],"fan-out-of-four":[54],"(FO4)":[55],"inverter":[56],"delays":[57],"integer":[59,111],"comprised":[61],"6":[63,83],"FO4":[64],"useful":[66],"work":[67],"an":[69],"overhead":[70],"about":[72],"2":[73,117],"FO4.":[74,84],"The":[75],"floating-point":[80],"benchmarks":[81],"We":[85],"these":[87,122],"points":[89],"to":[90,93,130,136],"be":[91,128],"insensitive":[92],"latch":[94],"skew":[97],"overheads.":[98],"Our":[99],"indicates":[101],"further":[103],"pipelining":[104],"can":[105],"at":[106],"best":[107],"improve":[108],"performance":[109],"programs":[112],"factor":[115],"current":[119],"designs.":[120],"At":[121],"high":[123],"frequencies":[125],"it":[126],"will":[127],"difficult":[129],"design":[131,149],"instruction":[133,153],"issue":[134],"window":[135],"operate":[137],"single":[140],"cycle.":[141],"Consequently,":[142],"propose":[144],"evaluate":[146],"high-frequency":[148],"called":[150],"segmented":[152],"window.":[154]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}